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CY2X013FLXIT Datasheet(PDF) 2 Page - Cypress Semiconductor |
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CY2X013FLXIT Datasheet(HTML) 2 Page - Cypress Semiconductor |
2 / 10 page CY2X013 Document Number: 001-10261 Rev. *G Page 2 of 10 Pinouts Figure 1. Pin Diagram – 6-Pin Ceramic LCC 1 3 OE/PD# VSS VDD CLK 6 4 2 5CLK# DNU Table 1. Pin Definitions - 6-Pin Ceramic LCC Pin Name I/O Type Description 1 OE/PD# CMOS input Output enable pin: Active HIGH. If OE = 1, CLK is enabled. Power-down pin: Active LOW. If PD# = 0, the device is powered down and the clock is disabled. The functionality of this pin is programmable 4, 5 CLK, CLK# LVDS output Differential output clock 2 DNU – Do not use: DNU pins are electrically connected, but perform no function 6VDD Power Supply voltage: 2.5 V or 3.3 V 3VSS Power Ground Standard and Application-Specific Factory Configurations Part Number Output Frequency Pin 1 Function RMS Phase Jitter (Random) Offset Range Jitter (Typical) CY2X013LXI062T 62.50 MHz OE 1.875 MHz to 20 MHz 12 kHz to 20 MHz 0.36 ps 0.96 ps CY2X013LXI100T 100.00 MHz OE 637 kHz to 10 MHz 900 kHz to 7.5 MHz 0.52 ps 0.39 ps CY2X013LXI122T 122.88 MHz OE 12 kHz to 20 MHz 0.81 ps CY2X013LXI125T 125.00 MHz OE 1.875 MHz to 20 MHz 12 kHz to 20 MHz 0.34 ps 0.84 ps CY2X013LXI156T 156.25 MHz OE 1.875 MHz to 20 MHz 0.31 ps CY2X013LXI200T 200.00 MHz OE 12 kHz to 20 MHz 0.74 ps [+] Feedback |
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