CY7C1021BNV33

Document #: 001-06433 Rev. *C

Page 7 of 17

Switching Characteristics[4]

Over the Operating Range

Parameter

Description

-15

Unit

Min

Max

READ CYCLE

Read Cycle Time

15

–

ns

Address to Data Valid

–

15

ns

Data Hold from Address Change

3

–

ns

CE LOW to Data Valid

–

15

ns

OE LOW to Data Valid

–

7

ns

OE LOW to Low Z

0

–

ns

OE HIGH to High Z[5, 6]

–

7

ns

CE LOW to Low Z[6]

3

–

ns

CE HIGH to High Z[5, 6]

–

7

ns

CE LOW to Power-Up

0

–

ns

CE HIGH to Power-Down

–

15

ns

Byte Enable to Data Valid

–

7

ns

Byte Enable to Low Z

0

–

ns

Byte Disable to High Z

–

7

ns

WRITE CYCLE[7]

Write Cycle Time

15

–

ns

CE LOW to Write End

10

–

ns

Address Set-Up to Write End

10

–

ns

Address Hold from Write End

0

–

ns

Address Set-Up to Write Start

0

–

ns

WE Pulse Width

10

–

ns

Data Set-Up to Write End

8

–

ns

Data Hold from Write End

0

–

ns

WE HIGH to Low Z[6]

3

–

ns

WE LOW to High Z[5, 6]

–

7

ns

Byte Enable to End of Write

9

–

ns

Notes

4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified

500 mV from steady-state voltage.

7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,

and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates

the write.

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