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K4T1G164QF

datasheet

DDR2 SDRAM

Rev. 1.11

K4T1G084QF

K4T1G044QF

1. Ordering Information

NOTE :

1. Speed bin is in order of CL-tRCD-tRP.

2. 12digit, "B" stands for flip chip FBGA PKG.

2. Key Features

Organization

DDR2-800 5-5-5

DDR2-800 6-6-6

DDR2-667 5-5-5

Package

256Mx4

K4T1G044QF-BCE7

K4T1G044QF-BCF7

K4T1G044QF-BCE6

60 FBGA

128Mx8

K4T1G084QF-BCE7

K4T1G084QF-BCF7

K4T1G084QF-BCE6

60 FBGA

64Mx16

K4T1G164QF-BCE7

K4T1G164QF-BCF7

K4T1G164QF-BCE6

84 FBGA

Speed

DDR2-800 5-5-5

DDR2-800 6-6-6

DDR2-667 5-5-5

Units

CAS Latency

5

6

5

tCK

tRCD(min)

12.5

15

15

ns

tRP(min)

12.5

15

15

ns

tRC(min)

57.5

60

60

ns

• 8 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5, 6

• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an

optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Special Function Support

- 50ohm ODT

- High Temperature Self-Refresh rate enable

85

• All of products are Lead-Free, Halogen-Free, and RoHS compliant

The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit

x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous

device achieves high speed double-data-rate transfer rates of up to 800Mb/

sec/pin (DDR2-800) for general applications.

The chip is designed to comply with the following key DDR2 SDRAM fea-

tures such as posted CAS with additive latency, write latency = read latency

- 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.

All of the control and address inputs are synchronized with a pair of exter-

nally supplied differential clocks. Inputs are latched at the crosspoint of dif-

ferential clocks (CK rising and CK falling). All I/Os are synchronized with a

pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-

ion. The address bus is used to convey row, column, and bank address

information in a RAS/CAS multiplexing style. For example, 1Gb(x8) device

receive 14/10/3 addressing.

The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply

The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in 84ball

FBGA(x16).

NOTE :

1. This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Dia-

gram”.

2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.