Rev. 1.1 November 2008

DDR SDRAM

K4H510438F

K4H510838F

K4H511638F

11 of 24

Conditions

Symbol

Operating current - One bank Active-Precharge;

tRC=tRCmin; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;

DQ,DM and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

IDD0

Operating current - One bank operation ; One bank open, BL=4, Reads

- Refer to the following page for detailed test condition

IDD1

Precharge power-down standby current; All banks idle; power - down mode;

Vin = Vref for DQ,DQS and DM.

IDD2P

6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle; Vin = Vref for

DQ,DQS and DM

IDD2F

IDD2Q

Active power - down standby current ; one bank active; power-down mode;

Vin = Vref for DQ,DQS and DM

IDD3P

one bank active; active - precharge; tRC=tRASmax; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;

DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock

cycle

IDD3N

Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control

inputs changing once per clock cycle; CL=2.5 at tCK=7.5ns for DDR266, tCK=6ns for DDR333, CL=3 at tCK=5ns

for DDR400; 50% of data changing on every transfer; lout = 0 m A

IDD4R

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle; CL=2.5 at tCK=7.5ns for DDR266, 6ns

for DDR333, 5ns for DDR400; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing

at every burst

IDD4W

Auto refresh current; tRC = tRFC(min) which is 16*tCK for DDR266 at tCK=7.5ns; 20*tCK for DDR333 at

tCK=6ns, 24*tCK for DDR400 at tCK=5ns; distributed refresh

IDD5

Self refresh current; CKE =< 0.2V; External clock on; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400.

IDD6

Operating current - Four bank operation ; Four bank interleaving with BL=4

-Refer to the following page for detailed test condition

IDD7A

Note :

1.These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.

This is required to match signal propagation times of DQ, DQS, and DM in the system.

3. Unused pins are tied to ground.

reflecting the fact that they are matched in loading (to facilitate trace matching at the board level).

Parameter

Symbol

Min

Max

DeltaCap(max)

Unit

Note

Input capacitance

(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)

23

0.5

pF

4

Input capacitance( CK, CK )

2

3

0.25

pF

4

Data & DQS input/output capacitance

45

0.5

pF

1,2,3,4

Input capacitance(DM for x4/8, UDM/LDM for x16)

4

5

pF

1,2,3,4

12.0 DDR SDRAM IDD Spec Items & Test Conditions

13.0 Input/Output Capacitance