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CY7C1150KV18 Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C1150KV18 Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 29 page CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 Document Number: 001-58912 Rev. *C Page 8 of 29 DOFF Input PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR I timing. TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/36M Input Not Connected to the Die. Can be tied to any voltage level. NC/72M Input Not Connected to the Die. Can be tied to any voltage level. NC/144M Input Not Connected to the Die. Can be tied to any voltage level. NC/288M Input Not Connected to the Die. Can be tied to any voltage level. VREF Input- reference Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. VDD Power supply Power supply Inputs to the Core of the Device VSS Ground Ground for the Device VDDQ Power supply Power Supply Inputs for the Outputs of the Device Table 2. Pin Definitions (continued) Pin Name I/O Pin Description [+] Feedback |
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Similar Description - CY7C1150KV18 |
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