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CY7C1250KV18-400BZC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C1250KV18-400BZC
Description  36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1250KV18-400BZC Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Document Number: 001-57834 Rev. *B
Page 5 of 28
Pin Configuration
The pin configuration for CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 follows.[2]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1246KV18 (4 M × 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
R/W
NWS1
K
NC/144M
LD
AA
CQ
B
NC
NC
NC
A
NC/288M
K
NWS0
ANC
NC
DQ3
C
NC
NC
NC
VSS
AAA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
AAA
VSS
NC
NC
NC
P
NC
NC
DQ7
A
A
QVLD
A
A
NC
NC
NC
R
TDO
TCK
AAA
NC
AAA
TMS
TDI
CY7C1257KV18 (4 M × 9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
R/W
NC
K
NC/144M
LD
AA
CQ
B
NC
NC
NC
A
NC/288M
K
BWS0
ANC
NC
DQ3
C
NC
NC
NC
VSS
AAA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
AAA
VSS
NC
NC
NC
P
NC
NC
DQ7
A
A
QVLD
A
A
NC
NC
DQ8
R
TDO
TCK
AAA
NC
AAA
TMS
TDI
Note
2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
[+] Feedback


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