CY7C1261KV18, CY7C1276KV18

CY7C1263KV18, CY7C1265KV18

Document Number: 001-57833 Rev. *C

Page 11 of 28

Truth Table

The truth table for CY7C1261KV18, CY7C1276KV18, CY7C1263KV18, and CY7C1265KV18 follows. [3, 4, 5, 6, 7, 8]

Operation

K

RPS WPS

DQ

DQ

DQ

DQ

Write cycle:

Load address on the rising

edge of K; input write data

on two consecutive K and

K rising edges.

L–H

H [9] L [10] D(A) at K(t + 1)

 D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)

Read cycle:

(2.5 cycle latency)

Load address on the rising

edge of K; wait two and

half cycles; read data on

two consecutive K and K

rising edges.

L–H

L [10]

X

Q(A) at K(t + 2)

 Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4)

NOP: No operation

L–H

H

H

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

Standby: Clock stopped

Stopped

X

X

Previous state

Previous state

Previous state

Previous state

Write Cycle Descriptions

The write cycle description table for CY7C1261KV18 and CY7C1263KV18 follows. [3, 11]

K

K

Comments

L

L

L–H

–

During the data portion of a write sequence



CY7C1261KV18

CY7C1263KV18

L

L

–

L–H During the data portion of a write sequence



CY7C1261KV18

CY7C1263KV18

L

H

L–H

–

During the data portion of a write sequence



CY7C1261KV18

CY7C1263KV18

L

H

–

L–H During the data portion of a write sequence



CY7C1261KV18

CY7C1263KV18

H

L

L–H

–

During the data portion of a write sequence



CY7C1261KV18

CY7C1263KV18

H

L

–

L–H During the data portion of a write sequence



CY7C1261KV18

CY7C1263KV18

H

H

L–H

–

No data is written into the devices during this portion of a write operation.

H

H

–

L–H No data is written into the devices during this portion of a write operation.

Notes

3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

4. Device powers up deselected with the outputs in a tristate condition.

5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.

6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.

8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the

second read or write request.

portions of a write cycle, as long as the setup and hold requirements are achieved.

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