CY7C1316KV18, CY7C1916KV18

CY7C1318KV18, CY7C1320KV18

Document Number: 001-58905 Rev. *C

Page 11 of 32

Truth Table

The truth table for the CY7C1316KV18, CY7C1916KV18, CY7C1318KV18, and CY7C1320KV18 follow.[2, 3, 4, 5, 6, 7]

Operation

K

LD

R/W

DQ

DQ

Write cycle:

Load address; wait one cycle;

input write data on consecutive K and K rising edges.

L–H

L

L

D(A1) at K(t + 1)

 D(A2) at K(t + 1) 

Read cycle:

Load address; wait one and a half cycle;

read data on consecutive C and C rising edges.

L–H

L

H

Q(A1) at C(t + 1)

 Q(A2) at C(t + 2) 

NOP: No operation

L–H

H

X

High Z

High Z

Standby: Clock stopped

Stopped

X

X

Previous State

Previous State

Burst Address Table

(CY7C1318KV18, CY7C1320KV18)

First Address (External)

Second Address (Internal)

X..X0

X..X1

X..X1

X..X0

Write Cycle Descriptions

The write cycle description table for CY7C1316KV18 and CY7C1318KV18 follows.[2, 8]

K

K

Comments

L

L

L–H

–

During the data portion of a write sequence



CY7C1316KV18

both nibbles (D

CY7C1318KV18

both bytes (D

L

L

–

L–H During the data portion of a write sequence



CY7C1316KV18

both nibbles (D

CY7C1318KV18

both bytes (D

L

H

L–H

–

During the data portion of a write sequence



CY7C1316KV18

only the lower nibble (D

CY7C1318KV18

only the lower byte (D

L

H

–

L–H During the data portion of a write sequence



CY7C1316KV18

only the lower nibble (D

CY7C1318KV18

only the lower byte (D

H

L

L–H

–

During the data portion of a write sequence



CY7C1316KV18

only the upper nibble (D

CY7C1318KV18

only the upper byte (D

H

L

–

L–H During the data portion of a write sequence



CY7C1316KV18

only the upper nibble (D

CY7C1318KV18

only the upper byte (D

H

H

L–H

–

No data is written into the devices during this portion of a write operation.

H

H

–

L–H No data is written into the devices during this portion of a write operation.

Notes

2. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW,



3. Device powers up deselected with the outputs in a tristate condition.

4. On CY7C1318KV18 and CY7C1320KV18, ‘A1’ represents address location latched by the devices when transaction was initiated and ‘A2’ represents the addresses

sequence in the burst. On CY7C1316KV18 and CY7C1916KV18, ‘A1’ represents A + ‘0’ and ‘A2’ represents A + ‘1’.

5. ‘t’ represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the ‘t’ clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

different portions of a write cycle, as long as the setup and hold requirements are achieved.

[+] Feedback