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K4B1G0446D Datasheet(PDF) 3 Page - Samsung semiconductor |
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K4B1G0446D Datasheet(HTML) 3 Page - Samsung semiconductor |
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3 / 60 page  Page 3 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAM K4B1G04(08/16)46D 1.0 Ordering Information ................................................................................................................... 5 2.0 Key Features ................................................................................................................................ 5 3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6 3.1 x4 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls) ..................... 6 3.2 x8 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls) ..................... 7 3.3 x16 Package Pinout (Top view) : 100ball FBGA Package(96balls + 4 balls of support balls) ................. 8 3.4 FBGA Package Dimension (x4/x8) ................................................................................................. 9 3.5 FBGA Package Dimension (x16) .................................................................................................. 10 4.0 Input/Output Functional Description ....................................................................................... 11 5.0 DDR3 SDRAM Addressing ........................................................................................................ 12 6.0 Absolute Maximum Ratings ...................................................................................................... 13 6.1 Absolute Maximum DC Ratings ................................................................................................... 13 6.2 DRAM Component Operating Temperature Range ......................................................................... 13 7.0 AC & DC Operating Conditions ................................................................................................ 13 7.1 Recommended DC operating Conditions (SSTL_1.5) ...................................................................... 13 8.0 AC & DC Input Measurement Levels ........................................................................................ 14 8.1 AC and DC Logic input levels for single-ended signals .................................................................. 14 8.2 VREF Tolerances ........................................................................................................................ 15 8.3 AC and DC Logic Input Levels for Ditterential Signals .................................................................... 16 8.3.1 Differential signal definition ................................................................................................ 16 8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .............................. 16 8.3.3 Single-ended requirements for differential signals ................................................................. 17 8.4 Differential Input Cross Point Voltage .......................................................................................... 18 8.5 Slew Rate Definition for Single Ended Input Signals ...................................................................... 18 8.6 Slew rate definition for Differential Input Signals ........................................................................... 18 9.0 AC and DC Output Measurement Levels.................................................................................. 19 9.1 Single Ended AC and DC Output Levels ....................................................................................... 19 9.2 Differential AC and DC Output Levels .......................................................................................... 19 9.3.Single Ended Output Slew Rate ................................................................................................... 19 9.4 Differential Output Slew Rate ...................................................................................................... 20 9.5 Reference Load for AC Timing and Output Slew Rate ..................................................................... 20 9.6 Overshoot/Undershoot Specification ........................................................................................... 21 9.6.1 Address and Control Overshoot and Undershoot specifications ............................................. 21 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications ................................. 21 9.7 34 ohm Output Driver DC Electrical Characteristics ....................................................................... 22 9.7.1 Output Drive Temperature and Voltage sensitivity ................................................................. 23 9.8 On-Die Termination (ODT) Levels and I-V Characteristics ............................................................... 23 9.8.1 ODT DC electrical characteristics ........................................................................................ 24 9.8.2 ODT Temperature and Voltage sensitivity ............................................................................. 25 9.9 ODT Timing Definitions .............................................................................................................. 26 9.9.1 Test Load for ODT Timings ................................................................................................. 26 9.9.2 ODT Timing Definition ........................................................................................................ 26 Table Contents |
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