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CY8C3866PVI-066 Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY8C3866PVI-066 Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 129 page PSoC® 3: CY8C38 Family Data Sheet Document Number: 001-11729 Rev. *R Page 10 of 129 Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance 3. Pin Descriptions IDAC0, IDAC1, IDAC2, IDAC3 Low resistance output pin for high current DACs (IDAC). OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out High current output of uncommitted opamp[12]. Extref0, Extref1 External reference input to the analog system. OpAmp0–, OpAmp1–, OpAmp2–, OpAmp3– Inverting input to uncommitted opamp. OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+ Noninverting input to uncommitted opamp. GPIO General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense[12]. I2C0: SCL, I2C1: SCL I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not required. I2C0: SDA, I2C1: SDA I2C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I2C SDA if wake from sleep is not required. Ind Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi 32.768-kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi 4- to 25-MHz crystal oscillator pin. nTRST Optional JTAG test reset programming and debug port connection to reset the JTAG connection. SIO Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWDCK Serial wire debug clock programming and debug port connection. SWDIO Serial wire debug input and output programming and debug port connection. SWV. Single wire viewer debug output. TCK JTAG test clock programming and debug port connection. TDI JTAG test data in programming and debug port connection. TDO JTAG test data out programming and debug port connection. Vddd Vssd Vdda Vssa Vssd Plane Vssa Plane Note 12. GPIOs with opamp outputs are not recommended for use with CapSense. [+] Feedback |
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