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CY8C21645-12PVXE Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY8C21645-12PVXE Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 36 page  CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Automotive PSoC® Programmable System-on-Chip™ Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-55397 Rev. *I Revised March 18, 2011 Features ■ Automotive Electronics Council (AEC) Q100 qualified ■ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 °C to +85 °C temperature range ❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 °C to +125 °C temperature range ■ Advanced peripherals (PSoC ® blocks) ❐ Six analog Type ‘E’ PSoC blocks provide: • Up to four comparators with digital-to-analog converters (DAC) references • Up to 10-bit single or dual analog-to-digital converters (ADCs) ❐ Up to eight digital PSoC blocks provide: • 8 to 32-bit timers, counters, and pulse width modulators (PWMs) • One-shot, multi-shot mode in timers and PWMs • PWM with deadband in one digital block • Shift register, cyclical redundancy check (CRC), and pseudo random sequence (PRS) modules • Full- or half-duplex UARTs • SPI masters or slaves, 8- to 16-bit variable data length • Connectable to all general-purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks ❐ Powerful synchronization support, analog module operations can be synchronized by digital blocks or external signals. ■ High-speed 10-bit successive approximation register (SAR) ADC with sample and hold optimized for embedded control ■ CY8C22345H devices integrate Immersion ® TouchSense® haptics technology for ERM drive control ■ Precision, programmable clocking ❐ Internal oscillator up to 24 MHz ❐ High accuracy 24 MHz with optional 32-kHz crystal and phase locked loop (PLL) ❐ Optional external oscillator, up to 24 MHz ❐ Internal low speed, low-power oscillator for watchdog and sleep functionality ■ Flexible on-chip memory ❐ Up to 16 KB flash program storage, 1000 erase/write cycles ❐ Up to 1 KB SRAM data storage ❐ In-System Serial Programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash ■ Optimized CapSense ® resource ❐ Supports two CapSense channels with simultaneous scanning ❐ Two current DACs provide programmable sensor tuning in firmware ❐ Two dedicated clock resources for CapSense ❐ Two dedicated 16-bit timers/counters for CapSense scanning ■ Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O combinations ■ Programmable pin configurations ❐ 25 mA sink, 10 mA drive on all GPIOs ❐ Pull-up, pull-down, high Z, strong, or open drain drive modes on all GPIOs ❐ Analog input on all GPIOs ❐ Configurable interrupt on all GPIOs ■ Additional system resources: ❐ I 2C master, slave, or multi-master • Operation up to 400 kHz • Hardware address detection feature ❐ Watchdog and sleep timers ❐ User-configurable low voltage detection ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference ❐ Hardware real time clock (RTC) block DIGITAL SYSTEM SRAM 1KB/512B Interrupt Controller Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) Global Digital Interconnect Global Analog Interconnect PSoC CORE CPU Core (M8C) SROM Flash 16K/8K Digital Block Array Multiply Accum. Internal Voltage Ref. Digital Clocks POR and LVD System Resets SYSTEM RESOURCES ANALOG SYSTEM Analog Ref Analog Input Muxing I 2C System Bus Analog Block Array Port 2 Port 1 Port 0 CapSense Digital Resources Port 3 Port 4 10-bit SAR ADC RTC Block Diagram [+] Feedback |
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