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CY25823 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY25823
Description  CK-SSCD Spread Spectrum Differential Clock Specification
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY25823 Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY25823
Document Number: 38-07579 Rev. *D
Page 9 of 15
CLKOUT/CLKOUT# Enable Clarification
The CLKOUT enable I2C register bit (Byte1, bit2) is used to
enable/disable the CLKOUT clock. The PLL and crystal oscillator
remains on when the outputs are disabled.
When CLKOUT is disabled, the disabled clock is three-stated.
The transition to this mode (three-state) is glitch free. Similarly,
when CLKOUT is enabled the clock starts in a predictable
manner without any glitches or abnormal behavior.
Current Reference, IREF
The details of the current reference circuit are shown in Figure 4.
The operational amplifier in the current reference circuit drives
the gate of MIREF with feedback to establish VREF = 1.1 V at both
inputs of the amplifier. Thus the reference current is established
according to the following formula:
IREF = 1.1 V / RREF
where RREF is the external resistor and 1.1 V is the reference
voltage.
The IREF is scaled by 6x at the output stage and IOUT is given as:
IOUT = 6 x IREF.
The recommended value for RREF is 475 Ohms, which corre-
sponds to the IREF of 2.32mA.
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Core Supply Voltage
–0.5
4.6
V
VDDA
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient
Functional
0
70
°C
TJ
Temperature, Junction
Functional
150
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
33.89
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
117.36
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
V
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Power supply for logic and outputs
3.3 ± 5%
3.135
3.465
V
VDDA
Power supply for PLL
3.3 ± 5%
3.135
3.465
V
VILI2C
Input Low Voltage
SDATA, SCLK
VSS–0.5
0.8
V
VIHI2C
Input High Voltage
SDATA, SCLK
2.0
VDD
V
VIL
Input Low Voltage
VSS – 0.5
0.8
V
VIH
Input High Voltage
2.0
VDD
V
IIL
Input Leakage Current
except internal pull-ups
resistors, 0 < VIN < VDD
–5
5
μA
IOZ
High-impedance Output Current
–10
10
μA
IDD
Dynamic Supply Current
without output load
50
mA
IDDS
Total Power Supply Current in Shutdown
mode (No Input Clock)
Shutdown active
250
μA
CIN
Input Pin Capacitance
2
5
pF
COUT
Output Pin Capacitance
3
6
pF
LIN
Input Pin Inductance
5
nH
RPU
SCLK and SDATA pull-up resistors
when PWRDWN = 1
50
200
k
Ω
RREF
IREF external reference resistor
1% tolerance
200
500
W
[+] Feedback


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