CY24130ZXC-2T datasheet(3/6 Pages) CYPRESS

Part #	CY24130ZXC-2T

Description	HOTLink II??SMPTE Receiver Training Clock

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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3 / 6 page

CY24130

Document #: 38-07711 Rev. *A

Page 3 of 6

Figure 2. Test and Measurement Setup

Voltage and Timing Definitions

Figure 3. Duty Cycle Definitions

Note

1. Not 100% tested.

DC Electrical Specifications

Parameter[1]

Name

Description

Min.

Typ.

Max.

Unit

IOH

Output High Current

VOH = VDD – 0.5, VDD/VDDL = 3.3V

12

24

–

mA

IOL

Output Low Current

VOL = 0.5, VDD/VDDL = 3.3V

12

24

–

mA

IIH

Input High Current

VIH = VDD

–5

10

μA

IIL

Input Low Current

VIL = 0V

–

10

μA

VIH

Input High Voltage

CMOS levels, 70% of VDD

0.7

–

V

VIL

Input Low Voltage

CMOS levels, 30% of VDD

––

0.3

V

IVDD

Supply Current

AVDD/VDD Current

–16–

mA

IVDDL

Supply Current

VDDL Current

–

14

–

mA

AC Electrical Specifications

Parameter[1]

Name

Description

Min.

Typ.

Max.

Unit

DC

Output Duty Cycle

Duty Cycle is defined in Figure 3; t1/t2, 50% of

VDD

45

50

55

%

ER

Rising Edge Rate

Output Clock Edge Rate, Measured from 20% to

80% of VDD, CLOAD = 15 pF. See Figure 4.

0.8

1.4

–

V/ns

EF

Falling Edge Rate

Output Clock Edge Rate, Measured from 80% to

20% of VDD, CLOAD = 15 pF. See Figure 4.

0.8

1.4

–

V/ns

t9

Clock Jitter

CLKA Peak-Peak Period Jitter

–

100

–

ps

t10

PLL Lock Time

–

3

ms

0.1

μF

VDDs

Outputs

CLOAD

GND

DUT

Clock

Output

V

DD

50% of V

DD

0V

t

1

t

2

[+] Feedback

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