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CYF0018V33L-133BGXI Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CYF0018V33L-133BGXI Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 29 page CYF0018V, CYF0036V CYF0072V Document Number: 001-53687 Rev. *H Page 5 of 29 Pin Definitions Pin Name I/O Pin Description D[35:0] Input Data inputs: Data inputs for a 36-bit bus Q[35:0] Output Data outputs: Data outputs for a 36-bit bus WEN Input Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers. REN Input Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers. IE Input Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This is used for 'write masking' or incrementing the write pointer without writing into a location. OE Input Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs are in High Z (high impedance) state. WCLK Input Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and into the configuration registers if LD is low. RCLK Input Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is high and from the configuration registers if LD is low. EF Output Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Output Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Output Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. It is synchronized to RCLK. PAF Output Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset value programmed into the FIFO. It is synchronized to WCLK. LD Input Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO RT Input Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. MRS Input Master reset: MRS initializes the internal read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the configuration registers are all set to default values and flags are reset. PRS Input Partial reset: PRS initializes the internal read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the configuration register settings are all retained and flags are reset. SPI_SCLK Input Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset registers if SPI_SEN is enabled. SPI_SI Input Serial input: Serial input data in SPI mode. SPI_SEN Input Serial enable: Enables serial loading of programmable flag offsets and configuration registers. MARK Input Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any subsequent retransmit operation resets the read pointer to this position. MB Input Mailbox: When asserted the reads and writes happen to flow-through mailbox register. TCK Input Test clock (TCK) Pin for JTAG TRST Input Reset pin for JTAG TMS Input Test mode select (TMS) pin for JTAG TDI Input Test data in (TDI) pin for JTAG TDO Output Test data out (TDO) for JTAG HF Output Half-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK. |
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