K6R4016V1D

CMOS SRAM

PRELIMPreliminaryPPPPPPPPPINARY

Rev 4.0

- 3 -

Mar. 2004

256K x 16 Bit High-Speed CMOS Static RAM

The K6R4016V1D is a 4,194,304-bit high-speed Static Random

Access Memory organized as 262,144 words by 16 bits. The

K6R4016V1D uses 16 common input and output lines and has

an output enable pin which operates faster than address

access time at read cycle. Also it allows that lower and upper

byte access by data byte control(UB, LB). The device is fabri-

cated using SAMSUNG

′s advanced CMOS process and

designed for high-speed circuit technology. It is particularly well

suited for use in high-density high-speed system applications.

The K6R4016V1D is packaged in a 400mil 44-pin plastic SOJ

or TSOP(II) forward or 48 TBGA.

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 8,10ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 20mA(Max.)

(CMOS) : 5mA(Max.)

1.2mA(Max.)L-Ver. only.

Operating K6R4016V1D-08 : 80mA(Max.)

K6R4016V1D-10 : 65mA(Max.)

• Single 3.3

±0.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention: L-Ver. only.

• Center Power/Ground Pin Configuration

• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16

• Standard Pin Configuration

K6R4016V1D-J : 44-SOJ-400

K6R4016V1D-K : 44-SOJ-400(Lead-Free)

K6R4016V1D-T : 44-TSOP2-400BF

K6R4016V1D-U : 44-TSOP2-400BF (Lead-Free)

K6R4016V1D-E : 48-TBGA with 0.75 Ball pitch

(7mm X 9mm)

• Operating in Commercial and Industrial Temperature range.

Clk Gen.

OE

UB

CS

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

1024 Rows

256 x 16 Columns

I/O Circuit &

Data

Cont.

WE

LB