Rev 1.1

512Kx36 & 1Mx18 SRAM

- 2 -

Jan. 2005

K7D161874B

K7D163674B

ORDERING INFORMATION

Part Number

Organization

Maximum

Frequency

K7D163674B-HC37

512Kx36

375MHz

K7D163674B-HC33

333MHz

K7D163674B-HC30

300MHz

K7D163674B-HC27

275MHz

K7D161874B-HC37

1Mx18

375MHz

K7D161874B-HC33

333MHz

K7D161874B-HC30

300MHz

K7D161874B-HC27

275MHz

GENERAL DESCRIPTION

The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as

524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung's advanced

CMOS technology.

Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At

the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after

write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and

falling edge of K clock for a double data rate (DDR) write operations.

Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling

edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access

time for all SDR and DDR operations.

The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is

9x17(153) Ball Grid Array balls on a 1.27mm pitch.

FEATURES

• 512Kx36 or 1Mx18 Organizations.

• HSTL Input and Outputs.

• Single Differential HSTL Clock.

• Synchronous Pipeline Mode of Operation with Self-Timed

Late Write.

• Free Running Active High and Active Low Echo Clock Output

Pin.

• Asynchronous Output Enable.

• Registered Addresses, Burst Control and Data Inputs.

• Registered Outputs.

• Double and Single Data Rate Burst Read and Write.

• Burst Count Controllable With Max Burst Length of 4

• Interleved and Linear Burst mode support

• Bypass Operation Support

• Programmable Impedance Output Drivers.

• JTAG Boundary Scan (subset of IEEE std. 1149.1)

• 153(9x17) Pin Ball Grid Array Package(14mmx22mm)