512Kx36 & 1Mx18 DDRII CIO b2 SRAM

- 2 -

Rev. 5.0 July 2006

K7I163682B

K7I161882B

Document Title

512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Revision History

Rev. No.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1.0

2.0

3.0

4.0

5.0

Remark

Advance

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

Preliminary

Final

Final

Final

Final

Final

History

1. Initial document.

1. Add the speed bin (-33, -30)

2. Delete the speed bin (-25, -13)

1. Change the Boundary scan exit order.

2. Correct the Overshoot and Undershoot timing diagram.

1. Add the speed bin (-25)

1. Correct the JTAG ID register definition

2. Correct the AC timing parameter (delete the tKHKH Max value)

1. Change the Maximum Clock cycle time.

2. Correct the 165FBGA package ball size.

1. Add the power up/down sequencing comment.

2. Update the DC current parameter (Icc and Isb).

3. Change the Max. speed bin from -33 to -30.

1. Change the ISB1.

1. Final spec release

1. Delete the x8 Org.

2. Delete the 300MHz speed bin

1. Add the Industrial temp. & Lead Free Package

1. Add the 300MHz speed bin

1. Change Vss/SA to NC/SA in Pin Configuration

Speed Bin

From

To

-30

200

230

-25

180

210

-20

160

190

-16

140

170

Draft Date

Oct. 23. 2002

Oct. 24. 2002

Dec. 16, 2002

Jan. 27, 2003

Mar. 20, 2003

April. 4, 2003

June. 20, 2003

Oct. 20. 2003

Oct. 31, 2003

Nov. 28, 2003

Nov. 10. 2004

Mar. 29. 2006

Jul. 26 2006