1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM

K7K3236U2C

K7K3218U2C

- 7 -

Rev. 1.0 August 2008

Programmable Impedance Output Buffer Operation

Depth Expansion

The allowable range of RQ is between 175

example, 250

Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates

are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. To guarantee

optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.

Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal for

each bank. Before chip deselected, all read and write pending operations are completed.

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are synchro-

nized with internal data output. Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.

Power-Up/Power-Down Supply Voltage Sequencing

Output Valid Pin (QVLD)

The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing

the data. QVLD is edge aligned with CQ and CQ.