K7R643682M

K7R641882M

K7R640982M

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Rev. 1.3 March 2007

The K7R643682M,K7R641882M and K7R640982M are 75,497,472-bits QDR (Quad Data Rate)

Synchronous Pipelined Burst SRAMs.

They are organized as 2,097,152 words by 36bits for K7R643682M, 4,194,304 words by 18 bits for K7R641882M and

8,388,608 words by 9bits for K7R640982M.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports

with the same cycle. Memory bandwidth is maximized as data can be transferred into SRAM on every rising edge of K and K,

and transferred out of SRAM on every rising edge of C and C.

And totally independent read and write ports eliminate the need for high speed bus turn around.

Address, data inputs, and all control signals are synchronized to the input clock (K or K).

Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high,

the data outputs are synchronized to the input clocks (K and K).

Read data are referenced to echo clock (CQ or CQ) outputs.

Read address is registered on rising edges of the input K clocks,

and write address is registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fixed to 2-bit sequential for both read and write operations.

Synchronous pipeline read and early write enable high speed operations.

Simple depth expansion is accomplished by using R and W for port selection.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

The K7R643682M,K7R641882M and K7R640982M are implemented with SAMSUNG's high performance 6T CMOS technology

and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 9-bit data words with each read command.

The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initiated with K clock rising edge.

And pipeline data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the R is disabled after a read operation, the K7R643682M,K7R641882M and K7R640982M will first complete burst read

operation before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

Write cycles are initiated by activating W at the rising edge of the positive input clock K.

Address is presented and stored in the write address register synchronized with following K clock.

For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 9-bit data words with each write command.

The first "early" data is transferred and registered in to the device synchronous with same K clock rising edge with W presented.

Next burst data is transferred and registered synchronous with following K clock rising edge.

Continuous write operations are initiated with K rising edge.

And "early writed" data is presented to the device on every rising edge of both K and K clocks.

When the W is disabled, the K7R643682M, K7R641882M, and K7R640982M will enter into deselect mode.

The device disregards input data presented on the same cycle W disabled.

The K7R643682M, K7R641882M and K7R640982M support byte write operations.

And in K7R640982M BW controls write operation to D0:D8.

Write Operations