KSZ8841-16MQL-EVAL datasheet(5/105 Pages) MICREL

Part #	KSZ8841-16MQL-EVAL

Description	Single-Port Ethernet MAC Controller with Non-PCI Interface

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Manufacturer	MICREL [Micrel Semiconductor]

Direct Link	http://www.micrel.com

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5 / 105 page

Micrel, Inc.

KSZ8841-16/32 MQL/MVL/MBL

October 2007

5

M9999-102207-1.6

Receive Queue (RXQ) Frame Format........................................................................................................................................ 39

EEPROM Interface ....................................................................................................................................................... 40

Loopback Support ........................................................................................................................................................ 42

Near-end (Remote) Loopback.................................................................................................................................................... 42

CPU Interface I/O Registers ............................................................................................................................................... 43

I/O Registers .............................................................................................................................................................................. 43

Internal I/O Space Mapping ....................................................................................................................................................... 44

Register Map: MAC and PHY ............................................................................................................................................. 52

Bit Type Definition ........................................................................................................................................................ 52

Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks) ................................................................ 52

Bank 0 Base Address Register (0x00): BAR................................................................................................................ 52

Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ........................................... 53

Bank 0 Bus Error Status Register (0x06): BESR ......................................................................................................... 53

Bank 0 Bus Burst Length Register (0x08): BBLR......................................................................................................... 53

Bank 1: Reserved ......................................................................................................................................................... 53

Bank 2 Host MAC Address Register Low (0x00): MARL ............................................................................................. 54

Bank 2 Host MAC Address Register Middle (0x02): MARM ........................................................................................ 54

Bank 2 Host MAC Address Register High (0x04): MARH ............................................................................................ 54

Bank 3 On-Chip Bus Control Register (0x00): OBCR .................................................................................................. 55

Bank 3 EEPROM Control Register (0x02): EEPCR ..................................................................................................... 55

Bank 3 Memory BIST Info Register (0x04): MBIR........................................................................................................ 56

Bank 3 Global Reset Register (0x06): GRR ................................................................................................................. 56

Bank 3 Power Management Capabilities Register (0x08): PMCR ............................................................................... 56

Bank 3 Wakeup Frame Control Register (0x0A): WFCR ............................................................................................. 57

Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0...................................................................................... 58

Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1...................................................................................... 58

Bank 4 Wakeup Frame 0 Byte Mask 0 Register (0x04): WF0BM0 .............................................................................. 58

Bank 4 Wakeup Frame 0 Byte Mask 1 Register (0x06): WF0BM1 .............................................................................. 58

Bank 4 Wakeup Frame 0 Byte Mask 2 Register (0x08): WF0BM2 .............................................................................. 58

Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3.............................................................................. 59

Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0...................................................................................... 59

Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1...................................................................................... 59

Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0 .............................................................................. 59

Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1 .............................................................................. 59

Bank 5 Wakeup Frame 1 Byte Mask 2 Register (0x08): WF1BM2 .............................................................................. 60

Bank 5 Wakeup Frame 1 Byte Mask 3 Register (0x0A): WF1BM3.............................................................................. 60

Bank 6 Wakeup Frame 2 CRC0 Register (0x00): WF2CRC0...................................................................................... 60

Bank 6 Wakeup Frame 2 CRC1 Register (0x02): WF2CRC1...................................................................................... 60

Bank 6 Wakeup Frame 2 Byte Mask 0 Register (0x04): WF2BM0 .............................................................................. 60

Bank 6 Wakeup Frame 2 Byte Mask 1 Register (0x06): WF2BM1 .............................................................................. 61

Bank 6 Wakeup Frame 2 Byte Mask 2 Register (0x08): WF2BM2 .............................................................................. 61

Bank 6 Wakeup Frame 2 Byte Mask 3 Register (0x0A): WF2BM3.............................................................................. 61

Bank 7 Wakeup Frame 3 CRC0 Register (0x00): WF3CRC0...................................................................................... 61

Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1...................................................................................... 61

Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0 .............................................................................. 62

Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1 .............................................................................. 62

Bank 7 Wakeup Frame 3 Byte Mask 2 Register (0x08): WF3BM2 .............................................................................. 62

Bank 7 Wakeup Frame 3 Byte Mask 3 Register (0x0A): WF3BM3.............................................................................. 62

Bank 8 – 15: Reserved ................................................................................................................................................. 62

Bank 16 Transmit Control Register (0x00): TXCR ....................................................................................................... 63

Bank 16 Transmit Status Register (0x02): TXSR......................................................................................................... 63

Bank 16 Receive Control Register (0x04): RXCR........................................................................................................ 64

Bank 16 TXQ Memory Information Register (0x08): TXMIR ........................................................................................ 64

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