Micrel, Inc.

MICRF008

August 2008

6

M9999-080108

Functional Diagram

ANT

VCC

VSS

SEL0

REFOSC

Ceramic

Resonator

CAGC

RF

Amp

mboer

1MHz

Programmable

Low-Pass

Filter

Peak

Detector

Reference

Oscillator

Synthesizer

Control

Logic

IF

Amp

IF

Amp

CTH

DO

OOK Demodulator

UHF Downconverter

Switched-Cap

Resistor

Reference and Control

AGC

Control

Figure 1. MICRF008 Block Diagram

Functional Description

The entire block diagram illustrates the basic structure of

the MICRF008YM. It is made of three sub-blocks, which

are the UHF Downconverter, the OOK Demodulator, and

the Reference and Control. Also shown in the figure are

two capacitors (CTH, and CAGC) and the reference

frequency device, usually a ceramic resonator. With the

exception of a supply decoupling capacitor and the

matching network on the antenna pin, these are all the

external components needed with the MICRF008YM to

make a complete UHF receiver. There is one control

input, the SEL0 pin. The purpose is to set the

demodulator filter bandwidth of either 2.4kHz or 4.8kHz,

and is set high or low according to the minimum pulse

width in the demodulated signal. The input is CMOS

compatible, and is pulled-up internally in the IC.

Receiver Operation

The MICRF008YM is a superheterodyne receiver

working in sweep mode. It is capable of data rates up to

9.6kbaud NRZ or 4.8kbaud Manchester encoded. The

MICRF008YM RF center frequency is controlled by a

completely integrated PLL/VCO frequency synthesizer

with frequency set by a ceramic resonator. The actual

swept bandwidth is approximately 3% of the RF carrier

frequency. It makes an ideal part to work with LC-based

transmitters or other types of transmitters that are not

precise in nature and vary their frequency with time. In

sweep mode the LO frequency (local oscillator) is varied

in a rate much higher than the data signal, which results

in down-conversion of approximately 3% of the carrier

frequency present at the antenna pin. The low level RF

signal is amplified by the RF amp section and

downconverted by the mixer to the IF frequency which is

amplified and filtered internally in the device and further

amplified for the peak detector. The peak detector will

detect the IF and further filtering is accomplished in the

programmable low-pass filter. The detected/filtered

signal is compared with the DC value of the

demodulated signal in the data-slicer and a digital output

is provided from the DO pin

Data Slicing Level

Extraction of the DC value of the demodulated signal for

purposes of logic-level data slicing is accomplished by

an external capacitor CTH and the on-chip switched-

capacitor resistor RSC, indicated in the block diagram.

The effective resistance of RSC scales inversely