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AN-1029 Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part # AN-1029
Description  Maximum Power Enhancement Techniques for SO-8 Power MOSFETs
Download  13 Pages
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

AN-1029 Datasheet(HTML) 3 Page - Fairchild Semiconductor

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3
Table 1: Thermal Board Configurations. Note: *Single device, **Dual devices.
R
θJA was calculated from the relationship between power and the change of junction temperature.
If readers are interested in the test conditions and method, they are encouraged to refer to appen-
dix B for details.
0
0.2
0.4
0.6
0.8
1
40
60
80
100
120
140
2oz COPPER MOU NT ING PAD AREA (in )
2
4.5"x5" FR-4 Board
T
= 25 C
S till Air
A
o
Top Cu*
Bottom Cu*
1/2T op+1/2Bottom Cu*
Top Cu**
* S ingle device
** Dual devices
Figure 3.
SO-8 Junction-to-Ambient thermal resistance versus copper mounting pad area and its
surface placement.
Plots in figure 3 show the relationship of R
θJA versus the copper mounting pad area and its surface
placement on the board. It is apparent that increasing copper mounting pad area considerably
lowers R
θJA from approximately 120 to 50
oC/W in the range from 0.006 to 1 square inches for single
device. In addition, placing all the copper on the top side of the board further reduces R
θJA by 5 to
10oC/W when compared with the other two placements.
By substituting the thermal resistance, ambient temperature, and the maximum junction tempera-
ture rating into equation 2.1, the steady-state maximum power dissipation curves can be obtained
and are shown in figure 4.
A 20% increase in the power handling can be achieved by increasing the copper pad area on top
of the board from 0.006 to 0.04 in2, layout 2. This thermal pad fits directly under the package, so
that no additional board space is required. For maximum performance, it is recommended to put
extra copper on the bottom of the board connected to the top pad by through-hole thermal vias.
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