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Differential Signaling

Differential signaling offers many advantages over single

ended technologies. LVDS signaling centers around 1.25V

with a 350 mV swing and is not dependent on power supply

voltage. Not only does this result in a faster, more stable

signal, it also makes migration to lower power supply volt-

ages much easier.

Another advantage to differential technology is that the bal-

anced differential lines have tightly coupled equal but polar

opposite signals which reduce EMI. The magnetic fields

radiated by each of the conductors are drawn toward each

other and cancel much of the magnetic fields.

Common Mode

Differential signaling also offers common mode rejection.

The receiver ignores any noise that is coupled equally on

to the differential signals and only considers the difference

between the two signals. The receiver has a common

mode voltage range of 0.05V to 2.35V. LVDS receivers will

operate with as much as a

r1V ground shift between the

driver and receiver. This is shown graphically in Figure 3.

Low swing differential signaling can also improve signal

integrity concerns at higher speeds. As throughput

demands increase throughout the information industry,

higher frequencies and wider bit widths cause transmission

line reflections and crosstalk. As system loading increases,

the characteristic impedance of a system can change and

cause impedance mismatches which will, in turn, send

reflective signals across the transmission line. These

reflections can cause bit errors or increase settling times

making timing budgets more difficult as speeds increase.

Differential signaling technologies like LVDS solve this by

accepting common mode noise on the differential line.

Additionally, lower swing differential technologies reduce

reflections by having small voltage swings which limit the

energy supplied to the transmission line.

FIGURE 3. Common Mode Noise Range

Failsafe

Failsafe is a feature offered in LVDS that will help system

reliability by preventing errors. Failsafe guarantees that the

outputs are in a known state (HIGH) when the receiver

inputs are under certain fault conditions. Without the fail-

safe feature, any external noise above receiver thresholds

could trigger the output to an unknown state.

According to the TIA/EIA-644 standard, when the receiver

inputs are open, not connected to the generator, or if the

generator is powered off, the failsafe feature will drive the

outputs high. If the receiver inputs are shorted, the outputs

will be in failsafe mode (HIGH State). The standard also

states that the receiver outputs will also go in to a failsafe if

the differential inputs remain within the threshold region for

an abnormal period of time.

This protection feature has many benefits for a system

designer. For instance, some applications may dictate that

not all of the LVDS receiver inputs are used. With the fail-

safe feature, the receiver outputs will always be in a known

state as long as the inputs are not receiving a valid signal.

Termination

Termination of LVDS is necessary at the receiver input to

EIA-644 specification stipulates an internal termination

resistor value between 90

: and 132:. Fairchild recom-

mends a termination resistor value between 90

: and 110:

depending on the characteristic impedance of the cable.

Termination of LVDS is much easier than most other tech-

nologies. ECL and PECL both use a 220

: pull-down resis-

tor on each driver output as well as a 100

: resistor across

the driver outputs. GTLP, due to the open drain configura-

tion, must have a termination resistor (usually 50

: double

terminated) to a 1.5V pull-up voltage in order to generate a

GTLP signal. (See Figure 4)