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FQA13N50C Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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FQA13N50C Datasheet(HTML) 7 Page - Fairchild Semiconductor |
7 / 17 page AN-8027 © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 8/26/09 7 To properly attenuate the twice line frequency ripple in VRMS, it is typical to set the poles around 10~20Hz. The resistor RIAC should be large enough to prevent saturation of the gain modulator as: . 2 159 MAX LINE BO IAC V GA R μ ⋅< (17) where VLINE.BO is the brownout protection line voltage, GMAX is the maximum modulator gain when VRMS is 1.08V (which can be found in the datasheet), and 159µA is the maximum output current of the gain modulator. (Design Example) The brownout protection threshold is 1.05V (VRMS-UVL) and 1.9V (VRMS-UVH), respectively. Then, the scaling down factor of the voltage divider is: 3 12 3 . 22 1.05 0.0162 72 22 RMS RMS UVL RMS RMS RMS LINE BO RV RR R V π π − =⋅ ++ =⋅ = Then the startup of the PFC stage at the minimum line voltage is checked as: .3 12 3 2 85 2 0.0162 1.95 1.9 LINE MIN RMS RMS RMS RMS VR V RR R ⋅ =⋅ ⋅ = > ++ The resistors of the voltage divider network are selected as RRMS1=2MΩ, RRMS1=200kΩ, and RRMS1=36kΩ. To place the poles of the low pass filter at 15Hz and 22Hz, the capacitors are obtained as: 1 3 12 11 53 2 2 15 200 10 RMS PRMS CnF fR ππ == = ⋅⋅ ⋅ ⋅ × 2 3 23 11 200 2 2 22 36 10 RMS PRMS CnF fR ππ ≅= = ⋅⋅ ⋅ ⋅ × The condition for Resistor RIAC is: . 66 2 272 9 5.8 159 10 159 10 MAX LINE BO IAC V R GM −− ⋅⋅ >⋅ = = Ω ×× Therefore, 6M Ω resistor is selected for RIAC. [STEP-4] PFC Inductor Design The duty cycle of boost switch at the peak of line voltage is given as: 2 BOUT LINE LP BOUT VV D V − = (18) Then, the maximum current ripple of the boost inductor at the peak of line voltage for low line is given as: . 22 1 LINE MIN BOUT LINE L BOOST BOUT SW VV V I L Vf − Δ= ⋅ ⋅ (19) The average of boost inductor current over one switching cycle at the peak of the line voltage for low line is given as: . . 2 OUT LAVG LINE MIN P I V η = ⋅ (20) Therefore, with a given current ripple factor (KRB=ΔIL/ILAVG), the boost inductor value is obtained as: 2 . 2 1 LINE MIN BOUT LINE BOOST RB OUT BOUT SW VV V L K PV f η ⋅− =⋅ ⋅ ⋅ (21) The maximum current of boost inductor is given as: . . 2 (1 ) (1 ) 22 PK OUT RB RB LL AVG LINE MIN P KK II V η =⋅ + = ⋅ + ⋅ (22) (Design Example) With the ripple current specification (40%), the boost inductor is obtained as: 2 . 23 2 1 85 0.82 387 2 85 10 524 0.4 300 387 65 LINE MIN BOUT LINE BOOST RB OUT BOUT SW VV V L KP V f H η μ − ⋅− =⋅ ⋅ ⋅ ⋅− ⋅ =⋅ ⋅ = ⋅ The average of boost inductor current over one switching cycle at the peak of the line voltage for low line is obtained as: . . 2 2 300 6.09 85 0.82 OUT LAVG LINE MIN P I A V η ⋅ == = ⋅⋅ The maximum current of the boost inductor is given as: . 2 (1 ) 2 2 300 0.4 (1 ) 7.31 85 0.82 2 PK OUT RB L LINE MIN PK I V A η =⋅ + ⋅ ⋅ =⋅ + = ⋅ [STEP-5] PFC Output Capacitor Selection The output voltage ripple should be considered when selecting the PFC output capacitor. Figure 14 shows the twice line frequency ripple on the output voltage. With a given specification of output ripple, the condition for the output capacitor is obtained as: , 2 BOUT BOUT LINE BOUT RIPPLE I C fV π > ⋅⋅ (23) where IBOUT is nominal output current of boost PFC stage and VBOUT,RIPPLE is the peak-to-peak output voltage ripple specification. The hold-up time also should be considered when determining the output capacitor as: 22 , BOUT HOLD BOUT BOUT BOUT MIN Pt C VV ⋅ > − (24) where PBOUT is nominal output power of boost PFC stage, tHOLD is the required holdup time, and VBOUT,MIN is the allowable minimum PFC output voltage during hold-up time. |
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