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LCBS-12-01 Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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LCBS-12-01 Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 30 page www.fairchildsemi.com © 2010 Fairchild Semiconductor Corporation 5 FEB279_FAN9611/12 • Rev. 0.0.2 3. Specifications This board has been designed and optimized for the following conditions: Input Voltage Range Rated Output Power Output Voltage (Rated Current) VIN Nominal : 85~264VAC VDD Supply : 13VDC~18VDC 400W 400V-1A Note: 1. Minimum output voltage during the 20ms hold-up time is 330VDC. VLINE = 85~264VAC VOUT = 400V fSW > 50kHz Efficiency > 96% down to 20% load (115VAC) Efficiency > 97% down to 20% load (230VAC) PF > 0.99 at full load The trip points for the built-in protections are set as below in the evaluation board. The non-latching output OVP trip point is set at 108% of the nominal output voltage. The latching output OVP trip point is set at 117% of the nominal output voltage. The line UVLO (brownout protection) trip point is set at 68VAC (10VAC hysteresis). The pulse-by-pulse current limit for each MOSFET is set at 9.1A. The maximum power limit is set at ~120% of the rated output power. The phase management function permits phase shedding/adding ~15% of the nominal output power for high line (230VAC). This level can be programmed by modifying MOT resistor (R6). |
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Similar Description - LCBS-12-01 |
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