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MBR05S0L Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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MBR05S0L Datasheet(HTML) 10 Page - Fairchild Semiconductor |
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10 / 15 page  © 2004 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5234 • Rev. 2.0.0 10 0 14 18 Modulator f P0 f Z f P Error amp. R1 R2 EA Out C1 C2 REF V IN Figure 7. Compensation kHz 6 C R 2 1 f 1 2 Z = π = (9) kHz 600 2 C R 2 1 f 2 P = π = (10) This region is also associated with phase “bump” or reduced phase shift. The amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90°. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp. The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency appears at the point where the modulator attenuation equals the amplifier high-frequency gain. The system designer must specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation, plenty of phase margin is achieved due to zero-pole pair phase “boost.” Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz to 50kHz range gives some additional phase boost. There is an opposite trend in mobile applications to keep the output capacitor as small as possible. Protections The converter output is monitored and protected against extreme overload, short circuit, over-voltage, and under-voltage conditions. A sustained overload on an output sets the PGOOD pin LOW and latches off the chip. Operation is restored by cycling the VCC voltage or by toggling the EN pin. If VOUT drops below the under-voltage threshold, the chip shuts down immediately. Over-Current Sensing If the circuit's current-limit signal (“ILIM det” in Figure 6) is HIGH at the beginning of a clock cycle, a pulse- skipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next eight clock cycles. If at any time from the ninth to the sixteenth clock cycle, the ILIM det is again reached, the over-current protection latch is set, disabling the chip. If ILIM det does not occur between cycles 9 and 16, normal operation is restored and the over-current circuit resets itself. 1 2 3 CH1 5.0V CH3 2.0AW CH2 100mV M 10.0s IL PGOOD 8 CLK VOUT Figure 8. Over-Current Protection Waveforms Over-Voltage / Under-Voltage Protection Should the VSEN voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure or for other reasons, the over-voltage protection comparator forces LDRV HIGH. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, eventually blows the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a ‘soft’ crowbar function to tackle severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. Similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point, the regulator shuts down. Over-Temperature Protection The chip incorporates an over-temperature protection circuit that shuts the chip down when a die temperature reaches 150°C. Normal operation is restored at die temperature below 125°C with internal power on reset asserted, resulting in a full soft-start cycle. |
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Similar Description - MBR05S0L |
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