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FAN5354 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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FAN5354 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 14 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5354 • Rev. 1.0.5 10 Operation Description The FAN5354 is a step-down switching voltage regulator that delivers an adjustable output from an input voltage supply of 2.7V to 5.5V. Using a proprietary architecture with synchronous rectification, the FAN5354 is capable of delivering 3A at over 80% efficiency. The regulator operates at a nominal frequency of 3MHz at full load, which reduces the value of the external components to 470nH for the output inductor and 20 F for the output capacitor. High efficiency is maintained at light load with single-pulse PFM mode. Control Scheme The FAN5354 uses a proprietary non-linear, fixed-frequency PWM modulator to deliver a fast load transient response, while maintaining a constant switching frequency over a wide range of operating conditions. The regulator performance is independent of the output capacitor ESR, allowing for the use of ceramic output capacitors. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency loop holds the switching frequency constant over a large range of input voltages and load currents. For very light loads, the FAN5354 operates in discontinuous current (DCM) single-pulse PFM mode, which produces low output ripple compared with other PFM architectures. Transition between PWM and PFM is seamless, with a glitch of less than 18mV at VOUT during the transition between DCM and CCM modes. The regulator limits minimum PFM frequency to typically26Khz. PFM mode can be disabled by holding the MODE pin HIGH. The IC synchronizes to the MODE pin frequency. When synchronizing to the MODE pin, PFM mode is disabled. Setting the output voltage The output voltage is set by the R1, R2, and VREF (0.8V): REF REF OUT V V V 2 R 1 R − = (1) R1 must be set at or below 100K ; therefore: ( ) 8 . 0 V 8 . 0 1 R 2 R OUT − • = (2) For example, for VOUT=1.2V, R1=100K , R2=200K . Enable and Soft Start When the EN pin is LOW, the IC is shut down, all internal circuits are off, and the part draws very little current. Raising EN above its threshold voltage activates the part and starts the soft-start cycle. During soft-start, the modulator’s internal reference is ramped slowly to minimize any large surge currents on the input and prevents any overshoot of the output voltage. If large values of output capacitance are used, the regulator may fail to start. If VOUT fails to achieve regulation within 320 µs from the beginning of soft-start, the regulator shuts down and waits 1200 µs before attempting a restart. If the regulator is at its current limit for more than about 60 µs, the regulator shuts down before restarting 1200 µs later. This limits the COUT capacitance when a heavy load is applied during the startup. For a typical FAN5354 starting with a resistive load: ) A ( I 100 400 ) F ( COUT LOAD MAX • − ≈ µ where LOAD OUT LOAD R V I = (3) Synchronous rectification is inhibited during soft-start, allowing the IC to start into a pre-charged load. MODE Pin – External Frequency Synchronization Logic 1 on this pin forces the IC to stay in PWM mode. A logic 0 allows the IC to automatically switch to PFM during light loads. If the MODE pin is toggled, the converter synchronizes its switching frequency to the frequency on the mode pin (fMODE). The MODE pin is internally buffered with a Schmitt trigger, which allows the MODE pin to be driven with slow rise and fall times. An asymmetric duty cycle for frequency synchronization is permitted as long as the minimum time below VIL(MAX) or above VIH(MAX) is 100ns. PGOOD Pin The PGOOD pin is an open-drain that pin indicates that the IC is in regulation when its state is open. PGOOD pulls LOW under the following conditions: 1. The IC has operated in cycle-by-cycle current limit for eight or more consecutive PWM cycles. 2. The circuit is disabled, either after a fault occurs, or when EN is LOW. 3. The IC is performing a soft-start. Under-Voltage Lockout When EN is HIGH, the under-voltage lockout keeps the part from operating until the input supply voltage rises high enough to properly operate. This ensures no misbehavior of the regulator during startup or shutdown. Input Over-Voltage Protection (OVP) When VIN exceeds VSDWN (about 6.2V) the IC stops switching to protect the circuitry from internal spikes above 6.5V. An internal 40 µs filter prevents the circuit from shutting down due to noise spikes. For the circuit to fully protect the internal circuitry, the VIN slew rate above 6.2V must be limited to no more than 15V/ms when the IC is switching. The IC protects itself if VIN overshoots to 7V during initial power-up as long as the VIN transition from 0 to 7V occurs in less than 10 µs (10% to 90%). Current Limiting A heavy load or short circuit on the output causes the current in the inductor to increase until a maximum current threshold is reached in the high-side switch. Upon reaching this point, the high-side switch turns off, preventing high currents from causing damage. 16 consecutive PWM cycles in current limit |
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