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MC68160CFB Datasheet(PDF) 5 Page - Motorola, Inc |
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MC68160CFB Datasheet(HTML) 5 Page - Motorola, Inc |
5 / 30 page MC68160 MC68160B MC68160C 5 MOTOROLA ANALOG IC DEVICE DATA Table 1. Pin Function Description (continued) Pin(s) Symbol Type Name/Function OSCILLATOR AND FREQUENCY MULTIPLIER 12 MFILT C Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be attached to this pin. 16 X1 I/C CMOS Oscillator Inverter Input and Crystal Connection Point: When connected for crystal oscillator operation, the frequency of the clock which appears at TCLK is half that of the crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an external 20 MHz CMOS compatible clock generator. 17 X2 O/C CMOS Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by an external CMOS Clock generator. MODE SELECT 3 4 5 CS0 CS1 CS2 I TTL Mode Select: The logic states applied to these pins select the appropriate interface for the desired IEEE–802.3 controller or enable the standby mode. When the standby mode is selected, the MC68160, B and C power supply current is greatly reduced. Additionally, in the standby mode, all of the controller inputs and outputs are driven to the high impedance state. 6 LOOP I TTL Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be Manchester encoded and then looped back through the Manchester decoder, appearing at the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP) or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI port transmits data from the controller while diagnostic loopback is selected. Likewise, the controller interface receives data neither from the TP nor the AUI receivers while in this mode. The polarity fault detection and link integrity functions are not inhibited by the diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is delivered following each transmission to simulate the twisted pair SQE test. 9 APORT I TTL Automatic Port Selection Enable: When high, MC68160, B and C will automatically select the TP or AUI port based on the presence or absence of valid link beats or frames at the TP receive input. If the AUI port is automatically selected, the MC68160, B and C will continue to produce link pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to resume normal operation. The power consumption is minimized in the circuitry associated with the unselected port. 27 TPSQEL I TTL Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the internal TP collision detect circuitry after each transmit operation to the TP media. This function provides a simulated collision to as much of the MC68160, B and C collision detect circuitry as possible without affecting the attached twisted pair channel. A normal SQE test results in a high logic state at the CLSN controller interface pin which begins 6 to 16–bit times after the last transition of a transmitted signal and continues for 5 to 15–bit times. (When the AUI port is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to the controller via the MC68160, B and C ACX+/– receive inputs) 28 TPFULDL I TTL Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit and receive operation on the twisted pair port without an indicated collision. This pin is not to be asserted with LOOP as a test mode is enabled that disrupts normal operation. 29 TPAPCE I TTL Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic polarity correction is enabled, and MC68160, B and C will internally correct for a polarity fault on the receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is indicated on TPPLR. 46 TPEN I/O TTL (TTL/CMOS) Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is manually selected, the MC68160, B and C will not produce link pulses for the TP port. If APORT is high, TPEN is an output which will indicate which port has been automatically selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink 10 mA in the low output state and source 10 mA in the high output state. (See Pin 9 Description.) Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to resume normal operation. The power consumption is minimized in the circuitry associated with the unselected port. In the standby mode, this pin is driven to the high impedance state. |
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