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R5F52105ADFP Datasheet(PDF) 4 Page - Renesas Technology Corp |
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R5F52105ADFP Datasheet(HTML) 4 Page - Renesas Technology Corp |
4 / 92 page R01DS0041EJ0050 Rev.0.50 Page 4 of 90 Apr 15, 2011 RX210 Group 1. Overview Under development Preliminary document Specifications in this document are tentative and subject to change. Communication function Serial communications interfaces (SCIc, SCId) 7 channels (channel 0, 1, 5, 6, 8, 9: SCIc, channel 12: SCId) Serial communications modes: Asynchronous, clock synchronous, and smart-card interface On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Average transfer rate clock can be input from TMR timers (SCL5, SCL6, and SCL12) Simple IIC Simple SPI Master/slave mode supported (SCId only) Start frame and information frame are included (SCId only) I2C bus interface (RIIC) 1 channel Communications formats: I2C bus format/SMBus format Master/slave selectable Supports the first mode Serial peripheral interface (RSPI) 1 channel RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock- synchronous operation (three lines) Capable of handling serial transfer as a master or slave Data formats Choice of LSB-first or MSB-first transfer The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Double buffers for both transmission and reception 12-bit A/D converter 12 bits (16 channels x 1 unit) 12-bit resolution Conversion time: 1.0 s per channel (in operation with ADCLK at 50 MHz) Operating modes Scan mode (single-cycle scan mode, continuous scan mode, and group scan mode) Sample-and-hold function Self-diagnosis for the A/D converter Assistance in detecting disconnected analog inputs Double-trigger mode (duplexing of A/D-converted data) A/D conversion start conditions Conversion can be started by software, a conversion start trigger from a timer (MTU2), an external trigger signal, or ELC. Temperature sensor Outputs the voltage that changes depending on the temperature PGA gain switchable: Four levels according to the voltage range D/A converter 2 channels 10-bit resolution Output voltage: 0 V to VREFH CRC calculator (CRC) CRC code generation for arbitrary amounts of data in 8-bit units Select any of three generating polynomials: X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1 Generation of CRC codes for use with LSB-first or MSB-first communications is selectable. Comparator A 2 channels Comparison of reference voltage and analog input voltage Comparator B 2 channels Comparison of reference voltage and analog input voltage Power supply voltage/ Operating frequency VCC = 1.62 to 5.5 V: 20 MHz (TBD), VCC = 2.7 to 5.5 V: 50 MHz Supply current TBD mA (typ.) Operating temperature 40 to +85C Package 100-pin TFLGA (PTLG0100JA-A) 100-pin LQFP (PLQP0100KB-A) 80-pin LQFP (PLQP0080KB-A) 80-pin LQFP (PLQP0080JA-A) 64-pin LQFP (PLQP0064KB-A) 64-pin LQFP (PLQP0064GA-A) Table 1.1 Outline of Specifications (3 / 3) Classification Module/Function Description |
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