R5F52105ADFF datasheet(2/92 Pages) RENESAS

Part #	R5F52105ADFF

Description	50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA

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Manufacturer	RENESAS [Renesas Technology Corp]

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R01DS0041EJ0050 Rev.0.50

Page 2 of 90

Apr 15, 2011

RX210 Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

1.

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different

packages.

Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will

differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.

Table 1.1

Outline of Specifications (1 / 3)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 50 MHz

 32-bit RX CPU

 Minimum instruction execution time: One instruction per state (cycle of the system clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Eight 32-bit registers

Accumulator: One 64-bit register

 Basic instructions: 73

 DSP instructions: 9

 Addressing modes: 10

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 x 32  64 bits

 On-chip divider: 32 / 32  32 bits

 Barrel shifter: 32 bits

Memory

ROM

 ROM capacity: 512 Kbytes (max.)

 Three on-board programming modes

Boot mode (The user mat and the user boot mat are programmable via the SCI.)

User boot mode

User program mode

 Parallel programmer mode (for off-board programming)

RAM

RAM capacity: 64 Kbytes (max.)

E2 data flash

E2 data flash capacity: 8 Kbytes

MCU operating mode

Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode

(software switching)

Clock

Clock generation circuit

 Main clock oscillator, sub-clock oscillator, Low-speed on-chip oscillator, high-speed on-chip oscillator,

PLL frequency synthesizer, and dedicated low-speed on-chip oscillator for IWDT

 Oscillation stop detection

 Measuring circuit for accurcy of clock frequency (clock-accurcy check: CAC)

 Independent frequency-division and multiplication settings for the system clock (ICLK), peripheral

module clock (PCLK), external bus clock (BCLK), and flashIF clock (FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 50 MHz (at max.)

Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at

max.)

Devices connected to the external bus run in synchronization with the external bus clock (BCLK):

12.5 MHz (at max.)

The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at

max.)

Reset

Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer

reset, deep software standby reset, and software reset

Voltage detection

Voltage detection circuit

(LVD)

 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels

Low power

consumption

Low power consumption

facilities

 Module stop function

 Four low power consumption modes

Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode

Interrupt

Interrupt control unit (ICU)

 Interrupt vectors: 117

 External interrupts: 9 (NMI and IRQ0 to IRQ7 pins)

 Non-maskable interrupts: 6 (the NMI pin, oscillation stop detection interrupt, voltage-monitoring

interrupt 1, voltage-monitoring interrupt 2, WDT interrupt, and IWDT interrupt)

 16 levels specifiable for the order of priority

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