R5F562TAEDFF datasheet(5/94 Pages) RENESAS

Part #	R5F562TAEDFF

Description	100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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5 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 5 of 92

Apr 20, 2011

RX62T Group

1. Overview

Communications

CAN module (CAN)

(as an optional

function)

 1 channel

 32 mailboxes

Serial peripheral

interface (RSPI)

 1 unit

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or to 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each

frame having up to 32 bits)

 Buffered structure

 Double buffers for both transmission and reception

LIN module (LIN)

 1 channel (LIN master)

 Supports revisions 1.3, 2.0, and 2.1 of the LIN protocol

A/D converter

12-bit A/D converter

(S12ADA)

 12 bits (2 units x 4 channels)

 12-bit resolution

 Conversion time:

1.0

s per channel (in operation with A/D conversion clock ADCLK at 50 MHz) for AVCC

= 4.0 to 5.5 V

2.0

s per channel (in operation with A/D conversion clock ADCLK at 25 MHz) for

AVCC0 = 3.0 to 3.6 V

 Two basic operating modes

Single mode and scan mode

 Scan mode

One-cycle scan mode

Continuous scan mode

2-channel scan mode (Input ports of the A/D unit are divided into two groups in this

mode, and the activation sources are separately selectable for each group.)

 Sample-and-hold function

A common sample-and-hold circuit for both units is included.

Additionally, sample-and-hold circuit for each unit is included. (three channels per unit)

 A/D-conversion register settings for each input pin.

 Two registers for the result of conversion are provided for a single analog input pin of

each unit (AN000 and AN100).

 Three ways to start A/D conversion

Conversion can be started by software, a conversion start trigger from a timer (MTU3 or

GPT), or an external trigger signal.

 Functionality for 8- or 10-bit precision output

Right-shifting of the results of conversion for output by two or four bits is selectable.

 Self-diagnostic function

The self-diagnostic function internally generates three analog input voltages (VREFL0,

VREFH0 x 1/2, VREFH0).

 Amplification of input signals by a programmable gain amplifier (three channels per unit)

Amplification rate: 2.0-, 2.5-, 3.077-, 3.636-, 4.0-, 4.444-, 5.0-, 5.714-, 6.667-, 10.0-, or

13.333-times amplification (a total of 11 steps)

 Window comparators (three channels per unit)

Table 1.1

Outline of Specifications (4 / 5)

Classification

Module/Function

Description

Similar Part No. - R5F562TAEDFF

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Renesas Technology Corp	R5F562TAADFF	640Kb / 25P	MCUs
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	R5F562TAADFP	640Kb / 25P	MCUs
	R5F562TABDFF	640Kb / 25P	MCUs

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R5F562TAEDFF Datasheet(PDF) 5 Page - Renesas Technology Corp

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