4Kb 1-Wire EEPROM with

200k Write/Erase Cycles

6

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AVAILABLE COMMANDS:

DATA FIELD AFFECTED:

READ ROM

MATCH ROM

SEARCH ROM

SKIP ROM

RESUME

OVERDRIVE-SKIP ROM

OVERDRIVE-MATCH ROM

64-BIT REG. #, RC-FLAG

64-BIT REG. #, RC-FLAG

64-BIT REG. #, RC-FLAG

RC-FLAG

RC-FLAG

RC-FLAG, OD-FLAG

64-BIT REG. #, RC-FLAG, OD-FLAG

1-Wire ROM

FUNCTION COMMANDS

WRITE SCRATCHPAD

READ SCRATCHPAD

COPY SCRATCHPAD

READ MEMORY

32-BYTE SCRATCHPAD, FLAGS

32-BYTE SCRATCHPAD

DATA MEMORY

DATA MEMORY

DS24B33-SPECIFIC

MEMORY FUNCTION COMMANDS

COMMAND LEVEL:

DS24B33

Figure 2. Hierarchical Structure for 1-Wire Protocol

MSB

8-BIT

CRC CODE

48-BIT SERIAL NUMBER

MSB

MSB

LSB

LSB

LSB

8-BIT FAMILY CODE

(23h)

MSB

LSB

Figure 3. 64-Bit Registration Number

registration number, 32-byte scratchpad, sixteen

32-byte pages of EEPROM, and a CRC-16 generator.

Figure 2 shows the hierarchical structure of the

1-Wire protocol. The bus master must first provide

one of the seven ROM (network) function commands:

Read ROM, Match ROM, Search ROM, Skip ROM,

Resume, Overdrive-Skip ROM, or Overdrive-Match

ROM. Upon completion of an overdrive ROM com-

mand byte executed at standard speed, the device

enters overdrive mode where all subsequent commu-

nication occurs at a higher speed. Figure 9

describes the protocol required for these ROM func-

tion commands. After a ROM function command is

successfully executed, the memory functions

become accessible and the master can provide any

one of the four memory function commands. Figure 7

describes the protocol for these commands. All data

is read and written least significant bit (LSB) first.

Parasite Power

Figure 1 shows the parasite power supply. This circuitry

“steals” power whenever the IO input is high. IO pro-

vides sufficient power as long as the specified timing

and voltage requirements are met.

64-Bit Registration Number

Each DS24B33 contains a unique registration number

that is 64 bits long. The first 8 bits are a 1-Wire family

code. The next 48 bits are a unique serial number. The

last 8 bits are a cyclic redundancy check (CRC) of the

first 56 bits. See Figure 3 for details. The 1-Wire CRC is

generated using a polynomial generator consisting of a

shift register and XOR gates as shown in Figure 4. The

about the 1-Wire CRC is available in Application Note

27:

Understanding and Using Cyclic Redundancy

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