DS28E10 datasheet(3/17 Pages) MAXIM

Part #	DS28E10

Description	1-Wire SHA-1 Authenticator Irreversible Write Protection

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Manufacturer	MAXIM [Maxim Integrated Products]

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1-Wire SHA-1 Authenticator

3

ABRIDGED DATA SHEET

ELECTRICAL CHARACTERISTICS (continued)

(TA = -40NC to +85NC, see Note 1.)

Note 1: Specifications at TA = -40NC are guaranteed by design only and not production tested.

Note 2: Refer to the full data sheet for this note.

Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested.

Note 4: System requirement.

Note 5: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery

times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.

For more heavily loaded systems, an active pullup such as that found in the DS2482-x00 might be required.

Note 6: Voltage below which, during a falling edge on IO, a logic 0 is detected.

Note 7: The voltage on IO needs to be less than or equal to VILMAX at all times while the master is driving IO to a logic 0 level.

Note 8: Voltage above which, during a rising edge on IO, a logic 1 is detected.

Note 9: After VIH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic 0.

Note 10: The I-V characteristic is linear for voltages less than 1V.

Note 11: Applies to a single DS28E10 attached to a 1-Wire line.

Note 12: The earliest recognition of a negative edge is possible at tREH after VIH has been reached on the preceding rising edge.

Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).

Note 14: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E10 present.

Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.

Note 15: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH. The actual

maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.

Note 16: d in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high

threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

Note 17: Data retention is degraded as TA increases.

Note 18: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to

data sheet limit at operating temperature range is established by reliability testing.

Note 19: Refer to the full data sheet for this note.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

IO PIN: 1-Wire READ

Read Low Time

(Notes 4, 16)

tRL

Standard speed

5

15 -

d

F

s

Overdrive speed

1

2 -

d

Read Sample Time

(Notes 4, 16)

tMSR

Standard speed

tRL + d

15

F

s

Overdrive speed

tRL + d

2

EPROM

Programming Current

IPROG

VPP = VPP(MAX) (Note 3)

Refer to the full data

sheet.

mA

Programming Time

tPP

ms

Programming Voltage

VPP

(Note 2)

V

Data Retention

tDR

At +85NC (Notes 17, 18)

10

Years

SHA-1 Engine

SHA-1 Computation Current

ICCSHA

VCC = 3.6V

Refer to the full data

sheet.

mA

SHA-1 Computation Time

tCSHA

(Note 19)

ms

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