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MAX7057ASE Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX7057ASE Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 20 page nates the problems associated with crystal-pulling FSK signal generation. The multiplying factor of the PLL is set by a 16-bit number, with 4 bits for integer and 12 bits for fraction. The 12-bit fraction in the synthesizer results in a tuning resolution that is equal to the refer- ence frequency divided by 4096. The MAX7057 has an internal variable shunt capacitor connected at the PA output. This capacitor is controlled using the SPI to maintain highly efficient transmission at any frequency within a 1.47 to 1 (28/19) tuning range. This means that it is possible to change the frequency and retune the antenna to the new frequency in a very short time. The combination of rapid-antenna tuning ability with rapid-synthesizer tuning makes the MAX7057 a true frequency-agile transmitter. The tuning capacitor has a resolution of 0.25pF. The MAX7057 also features adjustable output power through an exter- nal resistor to nearly +10dBm into a 50 Ω load at +2.7V. The MAX7057 supports data rates up to 100kbps NRZ in both ASK and FSK modes. In FSK mode, the fre- quency deviation can be programmed as low as ±2kHz and as high as ±100kHz. Power Amplifier (PA) The PA of the MAX7057 is a high-efficiency, open-drain switching-mode amplifier. In a switching-mode amplifi- er, the gate of the final-stage FET is driven with a very sharp 25% duty-cycle square wave at the transmit fre- quency. This square wave is derived from the synthe- sizer circuit. When the matching network is tuned correctly, the output FET resonates the attached match- ing circuit with a minimum amount of power dissipated in the FET. With a proper output-matching network, the PA can drive a wide range of antenna impedances, which include a small-loop PCB trace and a 50 Ω anten- na. The output-matching network suppresses the carri- er harmonics and transforms the antenna impedance to an optimal impedance at PAOUT, which is from 125 Ω to 250 Ω. When the output-matching network is properly tuned, the PA transmits power with a high overall efficiency of up to 25%. The efficiency of the PA itself is more than 39%. The output power can be adjusted by changing the impedance seen by the PA or by adjusting the value of an external resistor at PAOUT. Envelope Shaping The MAX7057 features an internal envelope-shaping resistor for ASK modulation, which connects between PAVDD and ROUT. When connected to the PA pullup inductor, the envelope-shaping resistor slows the turn- on/-off time of the PA and results in a smaller spectral width of the modulated PA output signal. Variable Capacitor The MAX7057 has a set of internal variable shunt capacitors that can be switched in and out to present different capacitor values at the PA output. The capaci- tors are connected from the PA output to ground. This allows changing the tuning network along with the syn- thesizer divide ratio each time the transmitted frequency changes, making it possible to maintain maximum trans- mitter power while moving rapidly from one frequency to another. When the particular capacitance control bit is high, the corresponding amount of shunt capacitance is added at PAOUT. The 32 capacitor values are selected using the SPI; the capacitance resolution is 0.25pF. The total capacitance can vary from 0 to 7.75pF. For example, if cap[1] and cap[3] are high, and cap[4], cap[2], and cap[0] are low, this circuit will add 2.5pF at PAOUT. See Table 1 for variable capacitor values and control bits. Fractional-N Phase-Locked Loop (PLL) The MAX7057 utilizes a fully integrated fractional-N PLL for its transmit frequency synthesizer. All PLL compo- nents, including the loop filter, are included on-chip. The loop bandwidth is programmable to either 300kHz or 600kHz. See Tables 2, 3, and 4 for “pllbw” bit description. The 16-bit fractional-N topology allows the transmit frequency to be adjusted in increments of fXTAL/4096. The allowable range of the fRF/fXTAL ratio is approximately 19 to 28. The fractional-N topology also allows exact FSK fre- quency deviations to be programmed, completely elimi- nating the problems associated with generating frequency deviations by crystal oscillator pulling. The integer and fractional portions of the PLL divider ratio set the transmit frequency. The following example shows how to determine the correct values to be loaded to registers HIFREQ1, HIFREQ0, LOFREQ1, and LOFREQ0. See Tables 2, 3, and 7–10 for a detailed description of these registers. 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter _______________________________________________________________________________________ 9 Table 1. Variable Capacitor Values and Control Bits SPI REGISTER BITS INCREMENTAL SHUNT CAPACITANCE (pF) cap[0] 0.25 cap[1] 0.5 cap[2] 1.0 cap[3] 2.0 cap[4] 4.0 |
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