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BTF50060-1TEA Datasheet(PDF) 10 Page - Infineon Technologies AG |
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BTF50060-1TEA Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 38 page Datasheet 10 Rev. 1.0, 2010-06-24 BTF50060-1TEA General Product Characteristics 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Figure 6 and Figure 7 are showing the typical thermal impedance of BTF50060-1TEA mounted according to Jedec JESD51-2,-5,-7 at natural convection on FR4 1s and 2s2p board. The product (chip + package) was simulated on a 76,4 x 114,3 x 1,5 mm board with 2 inner copper layers (2x 70µm Cu, 2 x 35µm Cu). Where applicable, a thermal via array under the exposed pad contacted the first inner copper layer. The PCB layer structure is shown in Figure 8. The PCB layout is shown in Figure 9. Table 4 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Thermal Resistance - Junction to Case R thJC 1) 1) Not subject to production test, specified by design. – 1 1.1 K/W – P_4.27 Thermal Resistance - Junction to Ambient - 2s2p R thJA_2s2p 1) –22 – K/W 2) 2) Specified R thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 mm Cu, 2 × 35 mm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_4.29 Figure 6 Typical Transient Thermal Impedance Zth(JA) =f(tP) for different cooling areas Figure 7 Typical Transient Thermal Impedance Zth(JA) =f(tP) for PWM operation with duty cycles D = t / tperiod on a 2s2p PCB W 3 >VHF@ VPLQIRRWSULQW VPPð VPPð VS W 3 >VHF@ ' VS |
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