Datasheet

10

Rev. 1.0, 2010-06-24

BTF50060-1TEA

General Product Characteristics

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Figure 6 and Figure 7 are showing the typical thermal impedance of BTF50060-1TEA mounted according to

Jedec JESD51-2,-5,-7 at natural convection on FR4 1s and 2s2p board. The product (chip + package) was

simulated on a 76,4 x 114,3 x 1,5 mm board with 2 inner copper layers (2x 70µm Cu, 2 x 35µm Cu). Where

applicable, a thermal via array under the exposed pad contacted the first inner copper layer. The PCB layer

structure is shown in Figure 8. The PCB layout is shown in Figure 9.

Table 4

Thermal Resistance

Parameter

Symbol

Values

Unit

Note /

Test Condition

Number

Min.

Typ.

Max.

Thermal Resistance -

Junction to Case

R

thJC

1)

1) Not subject to production test, specified by design.

–

1

1.1

K/W

–

P_4.27

Thermal Resistance -

Junction to Ambient - 2s2p

R

thJA_2s2p

1)

–22

–

K/W

2)

2) Specified

R

(Chip+Package) was simulated on a 76.2

× 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 mm Cu, 2 × 35 mm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

P_4.29

Figure 6

Typical Transient Thermal Impedance

Figure 7

Typical Transient Thermal Impedance









 











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