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BTS5682E Datasheet(PDF) 10 Page - Infineon Technologies AG |
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BTS5682E Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 46 page SPOC - BTS5682E Electrical Characteristics Data Sheet 10 Rev. 1.0, 2008-01-22 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Thermal Resistance 4.1.21 Current through limp home input pin I LHI -0.75 -2.0 0.75 2.0 mA – t ≤ 2min. Temperatures 4.1.22 Junction temperature T j -40 150 °C– 4.1.23 Dynamic temperature increase while switching ∆T j –60 K – 4.1.24 Storage temperature T stg -55 150 °C– ESD Susceptibility 4.1.25 ESD resistivity OUT pins vs. VBB other pins incl. OUT vs. GND V ESD -4 -2 4 2 kV HBM 6) – – 1) Not subject to production test, specified by design. 2) Device mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. 3) In accordance to AEC Q100-012 and AEC Q101-006. 4) RI is the internal resistance of the load dump pulse generator. 5) Current limitation is a protection feature. Operation in current limitation is considered as “outside” normal operating range. Protection features are not designed for continuous repetitive operation. 6) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5k Ω, 100pF). Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 4.2.1 Junction to Case 1) 1) Not subject to production test, specified by design. R thJC –– 2K/W – 4.2.2 Junction to Ambient 1) R thJA –22 – K/W 2) 2) Device mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. Absolute Maximum Ratings (cont’d)1) T j = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions min. max. |
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