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other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.

FEATURES 

LOW DRIFT 

LOW NOISE 

LOW PINCHOFF 

ABSOLUTE MAXIMUM RATINGS  

@ 25°C (unless otherwise noted) 

Maximum Temperatures 

Storage Temperature ‐65°C to +150°C 

Operating Junction Temperature 

+150°C 

Maximum Voltage and Current for Each Transistor – Note 1 

Gate Voltage to Drain or Source 

50V 

Drain to Source Voltage 

50V 

Gate Forward Current 

10mA 

Maximum Power Dissipation 

Device Dissipation @ Free Air – Total                 300mW 

 

MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED

SYMBOL 

CHARACTERISTICS 

VALUE 

UNITS 

CONDITIONS 

DRIFT VS. 

TEMPERATURE 

10 

µV/°C 

OFFSET VOLTAGE 

5 

mV 

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

SYMBOL 

CHARACTERISTICS 

MIN. 

TYP. 

MAX. 

UNITS 

CONDITIONS 

Breakdown Voltage 

50 

60 

‐‐ 

V 

VDS = 0                  ID=1nA 

Gate‐To‐Gate Breakdown 

±50 

‐‐ 

‐‐ 

V 

 

TRANSCONDUCTANCE 

Full Conduction 

 

2000 

 

‐‐ 

 

7000 

 

µmho 

 

VDG= 10V         VGS= 0V      f = 1kHz 

Typical Operation 

1000 

‐‐ 

2000 

µmho 

     VDG= 15V         ID= 200µA    f = 1kHz 

Mismatch 

‐‐ 

0.6 

3 

%  

 

DRAIN CURRENT 

Full Conduction 

 

0.5 

 

‐‐ 

 

10 

 

mA 

 

Mismatch at Full Conduction 

‐‐ 

1 

5 

%  

 

GATE VOLTAGE 

Pinchoff voltage 

 

‐0.5 

 

‐‐ 

 

‐2.5 

 

V 

 

Operating Range 

‐‐ 

‐‐ 

‐2.3 

V 

 

GATE CURRENT 

Operating 

 

‐‐ 

 

‐4 

 

‐15 

 

pA 

 

High Temperature 

‐‐ 

‐‐ 

‐10 

nA 

 

At Full Conduction 

‐‐ 

‐‐ 

100 

pA 

High Temperature 

5 

5 

5 

pA 

 

OUTPUT CONDUCTANCE 

Full Conduction 

 

‐‐ 

 

‐‐ 

 

20 

 

µmho 

 

Operating 

‐‐ 

0.2 

2 

µmho 

 

CMR 

COMMON MODE REJECTION 

 

95 

 

‐‐ 

 

‐‐ 

 

dB 

 

 

NF 

NOISE 

Figure 

 

‐‐ 

 

‐‐ 

 

0.5 

 

dB 

f= 100Hz           NBW= 6Hz 

Voltage 

‐‐ 

20 

‐‐ 

nV/√Hz 

 

CAPACITANCE 

Input 

 

‐‐ 

 

‐‐ 

 

8 

 

pF 

 

Reverse Transfer 

‐‐ 

‐‐ 

1.5 

pF  

The LSU401 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET

LSU401

LOW NOISE, LOW DRIFT

MONOLITHIC DUAL

N-CHANNEL JFET

LSU401 Applications:

Wideband Differential Amps

High-Speed,Temp-Compensated Single-Ended

Input Amps

High-Speed Comparators

Impedance Converters and vibrations detectors.

The LSU401 is a high-performance monolithic dual

JFET featuring extremely low noise, tight offset voltage

and low drift over temperature specifications, and is

targeted for use in a wide range of precision

instrumentation applications. The LSU401 features a 5-

mV offset and 10-µV/°C drift. The LSU401 is a direct

replacement for discontinued Siliconix LSU401.

The 8 Pin P-DIP and 8 Pin SOIC provide ease of

manufacturing, and the symmetrical pinout prevents

improper orientation.

(See Packaging Information).

Linear Systems replaces discontinued Siliconix U401

Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired

PDIP / SOIC (Top View)

Available Packages:

LSU401 in PDIP / SOIC

LSU401 available as bare die

Micross Components Europe

Tel: +44 1603 788967