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PIC18F96J65 Datasheet(PDF) 11 Page - Microchip Technology |
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PIC18F96J65 Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 492 page  2011 Microchip Technology Inc. DS39762F-page 11 PIC18F97J60 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: This family introduces a new line of low-voltage devices with the foremost traditional advantage of all PIC18 microcontrollers – namely, high computational per- formance and a rich feature set at an extremely competitive price point. These features make the PIC18F97J60 family a logical choice for many high-performance applications where cost is a primary consideration. 1.1 Core Features 1.1.1 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F97J60 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These options include: • Two Crystal modes, using crystals or ceramic resonators. • Two External Clock modes, offering the option of a divide-by-4 clock output. • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes, which allows clock speeds of up to 41.667 MHz. • An internal RC oscillator with a fixed 31 kHz output which provides an extremely low-power option for timing-insensitive applications. The internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. 1.1.2 EXPANDED MEMORY The PIC18F97J60 family provides ample room for application code, from 64 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last 100 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The PIC18F97J60 family also provides plenty of room for dynamic application data with 3808 bytes of data RAM. 1.1.3 EXTERNAL MEMORY BUS In the unlikely event that 128 Kbytes of memory are inadequate for an application, the 100-pin members of the PIC18F97J60 family also implement an External Memory Bus (EMB). This allows the controller’s inter- nal program counter to address a memory space of up to 2 Mbytes, permitting a level of data access that few 8-bit devices can claim. This allows additional memory options, including: • Using combinations of on-chip and external memory up to the 2-Mbyte limit • Using external Flash memory for reprogrammable application code or large data tables • Using external RAM devices for storing large amounts of variable data 1.1.4 EXTENDED INSTRUCTION SET The PIC18F97J60 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize reentrant application code originally developed in high-level languages, such as C. 1.1.5 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. • PIC18F66J60 • PIC18F87J60 • PIC18F66J65 • PIC18F96J60 • PIC18F67J60 • PIC18F96J65 • PIC18F86J60 • PIC18F97J60 • PIC18F86J65 |
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