Analog Integrated Circuit Device Data

Freescale Semiconductor

7

33886

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

TIMING CHARACTERISTICS

PWM Frequency (20)

–

–

10

kHz

Maximum Switching Frequency During Active Current Limiting (21)

–

–

20

kHz

Output ON Delay (22)

V+ = 14 V

–

–

18

μs

Output OFF Delay (22)

V+ = 14 V

–

–

18

μs

Output Rise and Fall Time (23)

2.0

5.0

8.0

μs

Output Latch-OFF Time

15

20.5

26

μs

Output Blanking Time

12

16.5

21

μs

Output FET Body Diode Reverse Recovery Time (24)

100

–

–

ns

Disable Delay Time (25)

–

–

8.0

μs

–

4.0

–

μs

Power-OFF Delay Time

–

1.0

5.0

ms

Notes

20.

The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM

pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching

frequency. Refer to Typical Switching Waveforms, Figures 10 through 17, pp. 10–11.

21.

The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant

OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency.

22.

Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition

direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the

90% point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to

the 10% point of the output response signal. See Figure 4, page 8.

23.

Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 6, page 8.

24.

Parameter is guaranteed by design but not production tested.

25.

Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See

Figure 5, page 8.

26.

state latch-OFF. See Figures 8 and 9, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature

above 160

latch-OFF will occur. See Figure 7, page 8.