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SPD50P03LG Datasheet(PDF) 2 Page - Infineon Technologies AG |
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SPD50P03LG Datasheet(HTML) 2 Page - Infineon Technologies AG |
2 / 9 page SPD50P03L G Parameter Symbol Conditions Unit min. typ. max. Thermal characteristics Thermal resistance, junction - case R thJC - - 1 K/W R thJA minimal footprint - - 75 6 cm 2 cooling area2) -- 50 Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=-250 µA -30 - - V Gate threshold voltage V GS(th) V DS=V GS, I D=-250 µA -1 -1.5 -2 Zero gate voltage drain current I DSS V DS=-30 V, V GS=0 V, T j=25 °C - -0.1 -1 µA V DS=-30 V, V GS=0 V, T j=175 °C - -10 -100 Gate-source leakage current I GSS V GS=-20 V, V DS=0 V - -10 -100 nA Drain-source on-state resistance R DS(on) V GS=-4.5 V, I D=-30 A - 8.5 12.5 mΩ Drain-source on-state resistance R DS(on) V GS=-10 V, I D=-50 A - 5.7 7.0 Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=-50 A 47 94 - S 1) Current is limited by bondwire; with anR thJC=1 K/W the chip is able to carry 123 A. Values 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Thermal resistance, junction - ambient Rev. 1. 8 page 2 200 8-07-10 |
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