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TLE42744GV50 Datasheet(PDF) 5 Page - Infineon Technologies AG |
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TLE42744GV50 Datasheet(HTML) 5 Page - Infineon Technologies AG |
5 / 18 page Data Sheet 5 Rev. 1.1, 2010-01-13 TLE42744 Pin Configuration 3.3 Pin Assignment PG-SSOP-14 exposed pad Figure 3 Pin Configuration (top view) 3.4 Pin Definitions and Functions PG-SSOP-14 exposed pad Pin No. Symbol Function 1, 2, 3, 5, 6, 7 n.c. not connected can be open or connected to GND 4GND Ground 8, 10, 11, 12, 14 n.c. not connected can be open or connected to GND 9Q Output block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 7 13 I Input block to ground directly at the IC with a ceramic capacitor Pad – Exposed Pad connect to GND and heatsink area |
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