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SN75DP130SSRGZT Datasheet(PDF) 9 Page - Texas Instruments |
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SN75DP130SSRGZT Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 31 page  Driver VIterm 50 W 50 W Receiver D+ D- VD+ VD- VID VICM = (VD+ + VD-) Y Z VY VZ VOD = VY - VZ 100pF 100pF 0V to 2V 50 W 50 W VID = VD+ - VD- 2 VOCM = (VY + VZ) 2 VOCM DVOCM(ss) VOCM(pp) D+ D- 0V 20% tF tR 80% 0% 100% VOD SN75DP130 www.ti.com SLLSE57 – APRIL 2011 MAIN LINK ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AEQ(HBR) Equalizer gain for RBR/HBR 9 dB See Table 5 and Table 8 for EQ setting details; AEQ(HBR2) Equalizer gain for HBR2 18 dB Max value represents the typical value for the maximum configurable EQ setting AEQ(TMDS) Equalizer gain for TMDS 3 dB ROUT Driver output impedance 50 Ω RIN Input termination impedance 40 50 60 Ω VIterm Input termination voltage AC coupled; self-biased 0 2 V Steady state output VOCM(SS) 0 2 V common-mode voltage Change in steady state output ΔVOCM(SS) common-mode voltage between Tested in compliance to section 3.10 in CTS 1.1a 10 mVPP logic levels 20 mVRMS VOCM(PP) Output common-mode noise HBR2 30 mVRMS VSQUELCH Squelch threshold voltage Programable via I2C; default at 80mVpp typical 80 mVPP ITXSHORT Short circuit current limit Main Link outputs shorted to GND 50 mA MAIN LINK SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPD Propagation delay time See Figure 5 300 ps tSK(1) Intra-pair output skew Signal input skew = 0ps; dR = 2.7Gbps, VPRE = 0dB, 20 ps 800mVp-p, D10.2 clock pattern at device input; See tSK(2) Inter-pair output skew 100 ps Figure 6 VOD(L0); VPRE(L0); EQ = 8dB; clean source; minimum input Δtjit Total peak-to-peak residual jitter and output cabling; 1.62Gbps, 2.7Gbps, and 5.4Gbps 15 ps PRBS7 data pattern. Time from active DP signal turned off to ML output off with tsq_enter Squelch entry time 10 120 μs noise floor minimized tsq_exit Squelch exit time Time from DP signal on to ML output on 0 1 μs Figure 5. Main Link Test Circuit Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): SN75DP130 |
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