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TPS62360YZHT Datasheet(PDF) 3 Page - Texas Instruments

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Part # TPS62360YZHT
Description  Processor Supply with I2C Compatible Interface and Remote Sense
Download  51 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS62360YZHT Datasheet(HTML) 3 Page - Texas Instruments

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TPS62360, TPS62361B, TPS62362
www.ti.com
SLVSAU9
– MAY 2011
THERMAL INFORMATION
TPS6236x
THERMAL METRIC(1)
YZH
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance(2)
94.8
θJCtop
Junction-to-case (top) thermal resistance(3)
25
θJB
Junction-to-board thermal resistance(4)
60
°C/W
ψJT
Junction-to-top characterization parameter(5)
3.2
ψJB
Junction-to-board characterization parameter(6)
57
θJCbot
Junction-to-case (bottom) thermal resistance(7)
n/a
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp.
–40°C ≤ TA ≤ 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VIN
Input voltage range at VIN, AVIN
2.5
5.5
V
VDD
I2C and registers supply voltage range
1.15
3.6
V
ISD(AVIN)
Shutdown current into AVIN
EN = LOW, VDD = 0V
0.65
5
µA
TA = 25°C
0.5
1
µA
EN = LOW,
ISD(VIN)
Shutdown current into VIN
VDD = 0V
TA = 85°C
1
3
µA
ISD(VDD)
Shutdown current into VDD
EN = LOW, I2C bus idle
0.01
µA
PFM mode
56
µA
EN = HIGH,
Operating quiescent current into (AVIN +
Forced PWM
IQ
IOUT = 0mA,
VIN)
mode
180
µA
not switching
(Test Mode)
Input voltage falling, EN = High
2.3
2.45
V
VUVLO
Under voltage lock out at AVIN
Input voltage rising, EN = Low
1.3
V
VUVLO,HYST(AVI
Under voltage lock out hysteresis at AVIN
Input voltage rising
110
mV
N)
VDD,UVLO
Under voltage lock out at VDD
Input voltage falling
0.7
0.92
1.1
V
VUVLO,HYST(VD
Under voltage lock out hysteresis at VDD
Input voltage rising
50
mV
D)
LOGIC INTERFACE
High-level input voltage at EN, VSEL0,
VIH
1.2
V
VSEL1
Low-level input voltage at EN, VSEL0,
VIL
0.4
V
VSEL1
Signal transition time at EN, VSEL0,
trf
rising and falling edge
30
mV/
µs
VSEL1
VIH,I2C
High-level input voltage at SCL, SDA
0.7x VDD
V
VIL,I2C
Low-level input voltage at SCL, SDA
0.3x VDD
V
Copyright
© 2011, Texas Instruments Incorporated
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Product Folder Link(s): TPS62360 TPS62361B TPS62362


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