Electronic Components Datasheet Search |
|
TPS74001DPTR Datasheet(PDF) 3 Page - Texas Instruments |
|
TPS74001DPTR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 23 page TPS740xx www.ti.com SBVS091A – JUNE 2011 – REVISED JUNE 2011 THERMAL INFORMATION TPS74001DGK TPS74001DPT(3) THERMAL METRIC(1)(2) DGK (4 pin short) DPT UNITS 8 PINS 5 PINS θJA Junction-to-ambient thermal resistance(4) 136.9 30.0 θJCtop Junction-to-case (top) thermal resistance(5) 35.3 15.3 θJB Junction-to-board thermal resistance(6) 68.0 14.4 °C/W ψJT Junction-to-top characterization parameter(7) 0.9 0.6 ψJB Junction-to-board characterization parameter(8) 67.8 14.4 θJCbot Junction-to-case (bottom) thermal resistance(9) n/a 5.8 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. (3) Thermal data for the DGK and DPT packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) DPT only, the exposed pad is connected to the PCB ground layer through a 8 × 8 thermal via array. (b) i. DPT: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. ii. DGK: The top copper layer has a dedicated pattern of 5% copper coverage and the bottom copper layer has another decicated pattern of 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. (4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). (8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). (9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TPS740xx |
Similar Part No. - TPS74001DPTR |
|
Similar Description - TPS74001DPTR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |