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LX1688IPW-TR Datasheet(PDF) 8 Page - Microsemi Corporation |
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LX1688IPW-TR Datasheet(HTML) 8 Page - Microsemi Corporation |
8 / 16 page RangeMAX™ LX1688 PRODUCTION DATA SHEET Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 Copyright © 2001 Rev. 1.2, 2006-03-09 Multiple Lamp CCFL Controller TM ® DE TAILED DESCRIP T ION and may or may not be externally synchronized to the LCD video frame rate. It will directly gate the signal BRT. CPWM should not be used in this case. FAULT PIN The fault pin is a digital output that indicates that the maximum numbers of strike attempts has occurred without lamp ignition. In this condition the FAULT pin will go active high with typically 20mA drive capability. Holding the OLSNS pin low (<200mV) will also force timeout and activate the FAULT pin. When used as a master, fault condition true does not inhibit master clock outputs PHA_SYNC and RMP_RST. I_R PIN The run mode frequency of the output is one half the internal ramp frequency, which is proportional to a bias current set by resistor RI of 80.6K. The output frequency can thus be adjusted by varying the value of RI-R, the typical range from about 50K to 100K. Since there is some variation in the frequency due to change in the input supply (VDD) it is recommended that the value of RI-R be selected at the nominal input voltage. SLEEP MODE (ENABLE SIGNAL) AND SWITCHED VDD (VDDSW) Since the LX1688 can be used in portable battery operated systems, a very low power sleep mode is included. The IC will consume less than 10µA quiescent current from both the VDD and VDD_P pins combined, when the ENABLE pin is deactivated. The polarity of the ENABLE pin is programmable by the BEPOL input (see table 1). In addition the controller provides a switched supply pin VDDSW this output supplies at least 10mA at VDD ─ .2V for external circuitry. This output can be used to power additional circuitry that can be enabled with the controller. RMP_RST AND PHA_SYNC PIN TIMING REQUIREMENT WITH SLAVE MODE OPERATION When the LX1688 is configured for slave mode operation, and RMP_RST and PHA_SYNC is supplied from an external source, the signal timing should be met as outlined below. RMP_RST should be 2 times frequency of lamp frequency and duty should be 10 to 13%, and PHA_SYNC should be generated by divide by 2 of RMP_RST signal. Phase of these signals should be met the as shown, note the delay between the RMP_RST and PHA_SYNC signals: Min Typ Max Unit T1 150 250 nsec T2 10 13 % T3 49 50 51 % Tr, Tf 100 nsec T3 duty is 50% of operating frequency. T2 T1 T3 BIAS & TIM I NG EQUATIONS Formula 1: Triangular Wave Generator Frequency, FTRI [Hz] ) 25 ( 1 FTRI TRI I C R × × = Formula 2: Lamp Frequency (AOUT’s switching frequency), FLAMP [Hz] 12 200 1 FLAMP I R e- × = Formula 3: Minimum Current Error Amp Bandwidth, BWIEA_MIN [Hz] 000048 . 0 BWIEA_MIN ICOMP C = Formula 4: Minimum Voltage Error Amp Bandwidth, BWVEA_MIN [Hz] 000048 0 BWVEA_MIN VCOMP C . = Formula 5: Softstart time, TSS [sec] TSS VCOMP C , , × = 000 500 4 Formula 6: Minimum Power-on Reset Pulse Width, TMIN_POR [sec] 6 3 . 2 TMIN_POR POR C e × = |
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