CY2XF24

Document Number: 001-53146 Rev. *E

Page 4 of 17

Functional Description

The CY2XF24 is a PLL-based high-performance clock

generator. It uses an internal crystal oscillator as a reference,

The CY2XF24 comes configured for four different frequencies.

At power-on, the four configurations are transparently loaded

into an internal volatile memory which, in turn, controls the PLL.

bus. You can also configure the CY2XF24 with new output

frequencies by shifting new data into the internal memory.

Frequency margining is a common application for this feature.

One frequency is used for the standard operating mode of the

device, while additional frequencies are available for margin

testing, either during product development or in-system

manufacturing test.

temporary and are lost when power is removed from the device.

At power-on, the device returns to its original state.

The configuration for a particular frequency is stored in a 6-byte

block of memory, known as a word. The CY2XF24 has four such

words, labeled ‘Frequency Word 0’ through ‘Frequency Word 3’.

An additional register byte contains a 2-bit field, which selects

one of the four frequency words. By writing to this Select Byte,

you can switch back and forth between the four programmed

frequencies. The select byte can be configured to select any of

the four frequency words at power on.

When changing the output frequency, the frequency transition is

not guaranteed to be smooth. There can be frequency

excursions beyond the start frequency and the new frequency.

Glitches and runt pulses are possible, and time must be allowed

for the PLL to relock.

used to change any of the four frequency words. When writing

currently selected word. Instead, write one of the three

unselected words before changing the select byte to select that

new word.

Figure 2 shows how the frequency words are arranged and

selected.

Figure 2. Frequency Words

Configuration Software

Cypress provides CyClockWizard™ software that enables users

to create data values for shifting into the frequency words. This

software is required because the algorithm is too complicated to

be described here.

The user specifies the output frequency. The software then

calculates the bit stream for up to four frequency words, as

outlined by the register addresses for each word seen in

Figure 2.

Programming Description

The CY2XF24 is a programmable device. Before being used in

an application, it must be programmed with the output

frequencies and other variables described in Programming

Variables on page 5. Two different device types are available,

each with its own programming flow. They are described in the

following section.

Field-Programmable CY2XF24F

Field programmable devices are shipped unprogrammed and

must be programmed before being installed on a printed circuit

board (PCB). Customers use CyClockWizard™ Software to

specify the device configuration and generate a joint electron

devices engineering council (JEDEC - extension .jed)

programming file. Programming of samples and prototype

quantities is available using the CyClockWizard software along

with a CY3675-CLKMAKER1 CyClockMaker Clock Programmer

Kit with a CY3675-LCC6A socket adapter. Cypress’s value

added distribution partners also provide programming services.

Field programmable devices are designated with an ‘F’ in the

part number. They are intended for quick prototyping and

inventory reduction. The software and programmer kit hardware

can be downloaded from www.cypress.com by clicking the

hyperlinks above.

Standard and Application-Specific Factory Configurations

Part Number

Output Frequency

Frequency Word

RMS Phase Jitter (Random)

Offset Range

Jitter (Typical)

CY2XF24LXI625T

78.125 MHz

156.25 MHz

312.50 MHz

625.00 MHz (default)

0

1

2

3

1.875 MHz to 20 MHz

1.875 MHz to 20 MHz

1.875 MHz to 20 MHz

1.875 MHz to 20 MHz

0.37 ps

0.31 ps

0.29 ps

0.31 ps

Note

10h – 15h

Frequency Word 0

PLL

Frequency Word 1

Frequency Word 2

Frequency Word 3

16h – 1Bh

1Ch – 21h

22h – 27h

Select Byte

40h

00

01

10

11

Bits [1:0]

Register

Address

Sel

Control

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