CY2XF33

Document Number: 001-53148 Rev. *E

Page 6 of 12

Termination Circuits

Figure 2. LVDS Termination

AC Electrical Characteristics[5]

Parameter

Description

Condition

Min

Typ

Max

Unit

Output frequency[6]

–50

–

690

MHz

FSC

Frequency stability, commercial

devices[7]

–

–

±35

ppm

FSI

–

–

±55

ppm

AG

Aging, 10 years

–

–

–

±15

ppm

Output duty cycle

F

450 MHz, measured at zero crossing

45

50

55

%

F > 450 MHz, measured at zero

crossing

40

50

60

%

Output rise and fall time

20% and 80% of full output swing

–

0.35

1.0

ns

Startup time

Time for CLK to reach valid frequency

––

5

ms

Re-lock time

Time for CLK to reach valid frequency

from FS0 or FS1 pin change

––

1

ms

RMS phase jitter (random)

–

1

–

ps

Notes

5. Not 100% tested, guaranteed by design and characterization.

6. This parameter is specified in CyberClocks Online software.

CLK

CLK#

100

