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CY2XF33 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY2XF33 Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 12 page CY2XF33 Document Number: 001-53148 Rev. *E Page 6 of 12 Termination Circuits Figure 2. LVDS Termination AC Electrical Characteristics[5] Parameter Description Condition Min Typ Max Unit FOUT Output frequency[6] –50 – 690 MHz FSC Frequency stability, commercial devices[7] TA = 0 °C to 70 °C – – ±35 ppm FSI Frequency stability, industrial devices[7] TA = –40 °C to 85 °C – – ±55 ppm AG Aging, 10 years – – – ±15 ppm TDC Output duty cycle F 450 MHz, measured at zero crossing 45 50 55 % F > 450 MHz, measured at zero crossing 40 50 60 % TR, TF Output rise and fall time 20% and 80% of full output swing – 0.35 1.0 ns TLOCK Startup time Time for CLK to reach valid frequency measured from the time VDD = VDD(min) –– 5 ms TLFS Re-lock time Time for CLK to reach valid frequency from FS0 or FS1 pin change –– 1 ms TJitter() RMS phase jitter (random) fOUT = 106.25 MHz (12 kHz–20 MHz) – 1 – ps Notes 5. Not 100% tested, guaranteed by design and characterization. 6. This parameter is specified in CyberClocks Online software. 7. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage. CLK CLK# 100 |
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