CY7B993V, CY7B994V

High Speed Multi Phase PLL Clock Buffer

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document #: 38-07127 Rev. *J

Revised April 26, 2011

Features

(CY7B994V) Input/Output Operation

Reference Inputs

Functional Description

The CY7B993V and CY7B994V High-speed Multi-phase PLL

Clock Buffers offer user selectable control over system clock

functions. This multiple output clock driver provides the system

integrator with functions necessary to optimize the timing of

high-performance computer and communication systems.

These devices feature a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

Eighteen

configurable

outputs

each

drive

terminated

transmission lines with impedances as low as 50

 while delivering

minimal and specified output skews at LVTTL levels. The outputs are

arranged in five banks. Banks 1 to 4 of four outputs allow a divide

function of 1 to 12, while simultaneously allowing phase

adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One

of the output banks also includes an independent clock invert

function. The feedback bank consists of two outputs, which

allows divide-by functionality from 1 to 12 and limited phase

adjustments. Any one of these eighteen outputs can be

connected to the feedback input as well as driving other inputs.

Selectable reference input is a fault tolerance feature that allows

smooth change-over to secondary clock source, when the

primary clock source is not in operation. The reference inputs

and feedback inputs are configurable to accommodate both

LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

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