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CY7B994V-5BBXIT Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY7B994V-5BBXIT Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 18 page RoboClock CY7B993V, CY7B994V Document #: 38-07127 Rev. *J Page 11 of 18 Operating Current ICCI Internal Operating Current CY7B993V VCC = Max, fMAX[7] – 250 mA CY7B994V – 250 mA ICCN Output Current Dissipation/Pair[8] CY7B993V VCC = Max, CLOAD = 25 pF, RLOAD = 50 at VCC/2, fMAX –40 mA CY7B994V – 50 mA Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions Min Max Unit Capacitance Parameter Description Test Conditions Min Max Unit CIN Input Capacitance TA = 25C, f = 1 MHz, VCC = 3.3V – 5 pF Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] Parameter Description CY7B993/4V-2 CY7B993/4V-5 Unit Min Typ Max Min Typ Max fIN Clock Input Frequency CY7B993V 12 – 100 12 – 100 MHz CY7B994V 24 – 200 24 – 200 MHz fOUT Clock Output Frequency CY7B993V 12 – 100 12 – 100 MHz CY7B994V 24 – 200 24 – 200 MHz tSKEWPR Matched-Pair Skew[14, 15] – – 200 – – 200 ps tSKEWBNK Intrabank Skew[14, 15] – – 200 – – 250 ps tSKEW0 Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[14, 15] – – 250 – – 550 ps tSKEW1 Output-Output Skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall)[14, 15] – – 250 – – 650 ps tSKEW2 Output-Output Skew (invert to nominal of different banks, compared banks at same frequency, rising edge to falling edge aligned, other banks at same frequency)[14, 15] – – 250 – – 700 ps tSKEW3 Output-Output Skew (all output configurations outside of tSKEW1and tSKEW2)[14, 15] – – 500 – – 800 ps tSKEWCPR Complementary Outputs Skew (crossing to crossing, complementary outputs of the same bank)[14, 15, 16, 17] – – 200 – – 300 ps tCCJ1-3 Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) – 50 150 – 50 150 ps Peak tCCJ4-12 Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5, 6, 8, 10, 12) – 50 100 – 50 100 ps Peak tPD Propagation Delay, REF to FB Rise –250 – 250 –500 – 500 ps Notes 7. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B993V, fNOM = 200 MHz for CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. 8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of 25 pF terminated to 50 at VCC/2. 9. This is for non-three level inputs. 10. Assumes 25 pF Max load capacitance up to 185 MHz. At 200 MHz the Max load is 10 pF. 11. Both outputs of pair must be terminated, even if only one is being used. 12. Each package must be properly decoupled. 13. AC parameters are measured at 1.5V unless otherwise indicated. 14. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz. 15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 16. Complementary output skews are measured at complementary signal pair intersections. 17. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. [+] Feedback |
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