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CY7C132 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY7C132 Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 15 page  CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev. *G Page 6 of 15 Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) [8] Parameter Description 7C132-35 7C136-35 7C142-35 7C146-35 7C132-45 7C136-45 7C142-45 7C146-45 7C132-55 7C136-55 7C136A-55 7C142-55 7C146-55 Unit Min Max Min Max Min Max Read Cycle tRC Read Cycle Time 35 45 55 ns tAA Address to Data Valid[9] 35 45 55 ns tOHA Data Hold from Address Change 0 0 0 ns tACE CE LOW to Data Valid[9] 35 45 55 ns tDOE OE LOW to Data Valid[9] 20 25 25 ns tLZOE OE LOW to Low Z[7, 10] 33 3 ns tHZOE OE HIGH to High Z[7, 10, 11] 20 20 25 ns tLZCE CE LOW to Low Z[7, 10] 55 5 ns tHZCE CE HIGH to High Z[7, 10, 11] 20 20 25 ns tPU CE LOW to Power Up[7] 00 0 ns tPD CE HIGH to Power Down[7] 35 35 35 ns Write Cycle[12] tWC Write Cycle Time 35 45 55 ns tSCE CE LOW to Write End 30 35 40 ns tAW Address Setup to Write End 30 35 40 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Setup to Write Start 0 0 0 ns tPWE R/W Pulse Width 25 30 30 ns tSD Data Setup to Write End 15 20 20 ns tHD Data Hold from Write End 0 0 0 ns tHZWE R/W LOW to High Z [7] 20 20 25 ns tLZWE R/W HIGH to Low Z [7] 00 0 ns Busy/Interrupt Timing tBLA BUSY LOW from Address Match 20 25 30 ns tBHA BUSY HIGH from Address Mismatch[13] 20 25 30 ns tBLC BUSY LOW from CE LOW 20 25 30 ns tBHC BUSY HIGH from CE HIGH[13] 20 25 30 ns tPS Port Set Up for Priority 5 5 5 ns tWB R/W LOW after BUSY LOW[14] 00 0 ns tWH R/W HIGH after BUSY HIGH 30 35 35 ns tBDD BUSY HIGH to Valid Data 35 45 45 ns tDDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns tWDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns [+] Feedback |
Similar Part No. - CY7C132_11 |
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Similar Description - CY7C132_11 |
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